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112 Commits

Author SHA1 Message Date
Deepak Nibade
d2a5cf6e80 gpu: nvgpu: gp10b: fix sparse warnings of static symbol 
Fix sparse warnings of below type by making necessary
symbols static:

warning: symbol '<symbol>' was not declared. Should it be static?

Bug 200088648

Change-Id: I222bebd958e29b3a95d161f05a3052389200fc10
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/736663
GVS: Gerrit_Virtual_Submit
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
 2016-12-27 15:22:05 +05:30
Terje Bergstrom
4b02177fd3 gpu: nvgpu: gp10b: Make page mapping scatter aware 
Augment new page mapping code to be aware of scattered
buffers.

Bug 1605769

Change-Id: Ifdb326563d28ccf07fc4d3d76a24492a68493fe3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/734355
 2016-12-27 15:22:05 +05:30
Terje Bergstrom
ac0cd782ab gpu: nvgpu: gp10b: Implement new page table format 
Implement the 5-level Pascal page table format. It is enabled
only for simulation.

Change-Id: I6767fac8b52fe0f6a2e2f86312de5fc93af6518e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/682114
 2016-12-27 15:22:05 +05:30
Deepak Nibade
0158c38037 gpu: nvgpu: gp10b: fix sparse warnings of static symbol 
Fix sparse warnings of below type by making necessary
symbols static:

warning: symbol '<symbol>' was not declared. Should it be static?

Bug 200088648

Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/728012
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
 2016-12-27 15:22:05 +05:30
Deepak Nibade
9f22ad4687 gpu: nvgpu: add get_iova_addr() for gp10b 
Add platform specific gp10b_mm_iova_addr() to get
iova/phys address for gp10b

If SMMU is not enabled and IO coherence flag is set,
set 34th bit in the physical address and return the
physical address

If SMMU is enabled, return the iova address

Bug 1605653

Change-Id: I5c91a8c8d85d8a8e422406e3c91fc1dda3cb0870
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/713106
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:04 +05:30
Terje Bergstrom
e1339b8589 gpu: nvgpu: gp10b: Use mem_desc for buffers 
Change-Id: Ia986125bf1a6e06121291f6dde24e580f0a1b61f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/712836
 2016-12-27 15:22:04 +05:30
Terje Bergstrom
6539c538c1 gpu: nvgpu: gp10b: Use gp10b version of phys bits 
Use gp10b version of get_physical_addr_bits.

Change-Id: I56d1299e259e91a61fa82dc061e7ca3a5130b9d4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/714402
 2016-12-27 15:22:04 +05:30
Seshendra Gadagottu
8fe7abebbb gpu: nvgpu: gp10b: Add replayable pagefault buffer 
Add support for replayable fault buffer and enable it.

Bug 1587836

Change-Id: Iee4ba42ab175c0d72d2c041fdb3ac9d845358847
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/661668
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:04 +05:30
Seshendra Gadagottu
c965d7a54a gpu: nvgpu: gp10b: setup mm hw init 
Add support for gp10b specific mm hw init.

Bug 1587825

Change-Id: Iaccf1bf73468cfdd1842a001ab5e682ac06f1950
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/681787
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:04 +05:30
Seshendra Gadagottu
df6d5ab07b gpu: nvgpu: gp10b: Add Bar2 support 
Add bar2 support for gp10b and set-up bar2 binding.

Bug 1587825

Change-Id: I46660b3a28a5667ec782dd45b4528ae5f79e17c8
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/659236
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
945e5e6832 gpu: nvgpu: gp10b: Correct SMMU bit number 
Bit 36 is the correct bit to indicate SMMU translation.

Bug 1580756

Change-Id: I761e70265d5981b07940f1d43716416829993827
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/658827
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
c23f7708ac gpu: nvgpu: gp10b: Define physical address width 
GP10B physical address width is 37 bits. Use old width for now,
and add gp10b specific definition. We can switch to new definition
once we've verified them.

Bug 1567274

Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601703
 2016-12-27 15:22:02 +05:30