Commit Graph

4 Commits

Author SHA1 Message Date
Konsta Holtta
5cde4c2140 gpu: nvgpu: move chip specific channel reg ops to common
Extract out the HAL ops' implementation that now belongs to the channel
unit. This unit is responsible for channel register accesses and the
like (ccsr_*).

Rename channel_gm20b_bind to gm20b_fifo_channel_bind to match with the
rest of the naming. Same with channel_gv11b_unbind.

Jira NVGPU-1307

Change-Id: I58b9d96dbdaf36bdb163a5729544a41faec828ab
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017262
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-12 17:05:43 -08:00
David Nieto
1f71f475e2 DNI: gpu: nvgpu: Increase GV100 ctxsw timeouts
During bringup and before nvlink is up GV100 on the DDPX platform operates
with a very, very slow sysmem link. In order to get sysmem test to pass
it is neccesary to significantly increase most timeouts by an order the
magnitude.

Bug 2040544

Change-Id: I26858afde4ae80c70f86b47cfff674b6b00b5bf8
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1627417
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-01-05 13:54:37 -08:00
David Nieto
6114553413 gpu: nvgpu: gv100: fix timeout handling
GV100 has a larger vidmem size and a slower sideband to sysmem so timeouts
need to be adjusted to avoid false positives.

JIRA: NVGPUGV100-36

Change-Id: I3cbc19aa1158c89bc48ae1fa6ec4bc755cd9389d
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1582092
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-10-22 22:15:22 -07:00
David Nieto
f518304e0d gpu: nvgpu: fix GV100 hal definitions
These changes allow GV100 to init the basic HALs to pass
nvgpu_submit_twod

(1) Allocate fault buffer from vidmem instead of sysmem to prevent coherency
issues
(2) Properly enable FB
(3) Fan control requires the execution of the pre-os FW, without it the SKU201
is extremely noisy

 JIRA: NVGPUGV100-9

Change-Id: I9b2072737e45432f957e7faae6d33bc0ab43b817
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1539926
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-10-10 12:05:41 -07:00