Commit Graph

12 Commits

Author SHA1 Message Date
Amurthyreddy
89660dbd62 gpu: nvgpu: MISRA 14.4 bitwise operation as boolean
MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.

Fix violations where the result of a bitwise operation is used as a
boolean in the controlling expression of if and loop statements.

JIRA NVGPU-1020

Change-Id: If910150072c3dd67c31fe9819c3a9e738fd3c1c6
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1932389
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-26 10:06:55 -07:00
ddutta
8381eeea4f gpu: nvgpu: change location of gk20a.h#include <nvgpu/gk20a.h>
Update the include location of gk20a.h to include/nvgpu/gk20a.h in the
following directories.

nvgpu/gm20b/
nvgpu/gp10b/
nvgpu/gv11b/

Jira NVGPU-597

Change-Id: Ie38d4a72bb65c41bd30058350509bfa7e87bb64e
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822789
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-09-14 15:35:12 -07:00
Debarshi Dutta
82a90170d3 gk20a: nvgpu: Remove io.h dependency from gk20a.h
In the current code, gk20a.h includes io.h which gets directly included
in a lot of other files. io.h contains methods which uses a struct
gk20a as a parameter leading to a circular dependency between io.h
and gk20a.h. This can be mitigated by removing io.h from gk20a.h as
part of larger effort to moving gk20a.h to nvgpu/gk20a.h

JIRA NVGPU-597

Change-Id: I93e504fa9371b88152737b342a75580c65e8f712
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1787316
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-07-30 11:24:06 -07:00
Terje Bergstrom
d61643c020 gpu: nvgpu: gv11b: Change license for common files to MIT
Change license of OS independent source code files to MIT.

JIRA NVGPU-218

Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1567804
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-09-25 17:03:31 -07:00
seshendra Gadagottu
a42d6029a5 gpu: nvgpu: gv11b: correct logic to get num of pce
Correct the logic to get number of physical
copy engines supported in gv11b.

Change-Id: I02e0628364d056121d08dfcd0ddfb0c013207d4b
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1544207
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-09-01 03:19:41 -07:00
Sunny He
3c556c5e95 gpu: nvgpu: gv11b: Reorg ce2 HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the ce2
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: Ia2d715a471d7e23420691a461e9442780176ea13
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1509633
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-07-27 16:34:37 -07:00
Seema Khowala
66fb130bfd gpu: nvgpu: gv11b: recover from replay and ce mmu fault
Fix pte valid bit for replayable fault and ce fault

JIRA GPUT19X-12

Change-Id: I77a7a452d9b5b304f182e120e8d75959d46d4422
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1515538
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-12 07:44:49 -07:00
Seema Khowala
2f6d321390 gpu: nvgpu: gv11b: add mmu fault handling
HUB reports following memory sub-system interrupts:
a) ACCESS_COUNTER_NOTIFY:
   GET != PUT for access counter notify buffer
b) ACCESS_COUNTER_ERROR:
   HUB received a NACK (BAR2 fault) when writing the
   notify buffer out to memory
c) MMU_ECC_UNCORRECTED_ERROR_NOTIFY:
   Uncorrected ECC error detected by HUB MMU
d) MMU_REPLAYABLE_FAULT_NOTIFY:
   GET != PUT for replayable fault buffer
e) MMU_REPLAYABLE_FAULT_OVERFLOW:
   Overflow when writing to the replayable fault buffer
f) MMU_NONREPLAYABLE_FAULT_NOTIFY:
   GET != PUT for non-replayable fault buffer
g) MMU_NONREPLAYABLE_FAULT_OVERFLOW:
   Overflow when writing to the non-replayable fault buffer
h) MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU

This change is to :
-Detect other fault notify
-Copy fault info from fault snap register for other fault notify
 interrupt
-Detect and handle nonreplay/replay fault notify and fault overflow
-Copy fault info from fault buffer for nonreplay/replay fault
-Print fault info

JIRA GPUT19X-7
JIRA GPUT19X-12

Change-Id: Ifa08a4ebcd119a7d81c2eae3f52dc825d1ce3898
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1493394
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-07-08 11:35:48 -07:00
Seema Khowala
5a57be6ba1 gpu: nvgpu: gv11b: init get_num_pce ce ops
Implement get_num_pce ce ops to get number of physical
copy engines. This is required to calculate eng method
buffer size

JIRA GPUT19X-46

Change-Id: I5a37eb26ec11bc358700d1761cfdb6ca060e4287
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1511788
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-07-02 10:20:08 -07:00
Seema Khowala
f525ff15c4 gpu: nvgpu: gv11b: add ce interrupt handling
Added handling for below ce interrupts
-INVALID_CONFIG interrupt will be generated if a floorswept
 PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG
 registers. This is a fatal error and the LCE will have to be
 reset to get back to a working state.

-MTHD_BUFFER_FAULT interrupt will be triggered if any access to
 a method buffer during context load or save encounters a fault.
 This is a fatal interrupt and will require at least the LCE to be reset
 before operations can start again, if not the entire GPU.

JIRA GPUT19X-12
JIRA GPUT19X-46

Change-Id: I2eeefc4e634f5bf53f20933c493c7594fe0ea755
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1510298
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-07-02 10:20:07 -07:00
Alex Waterman
4b09997772 nvgpu: gpu: HW header update for Volta
Similar HW header update as has been done for all the other chips.
HW header files are located under:

  drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/

And can be included like so:

  #include <nvgpu/hw/gv11b/hw_gr_gv11b.h>

Bug 1799159

Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1284433
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-24 15:15:16 -08:00
Lakshmanan M
6f24a76660 gpu: nvgpu: Add multiple engine and runlist support
This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt support for
   Volta GPU series
5) Removed hard coded engine_id logic and
   made generic way
6) Code cleanup for readability

JIRA DNVGPU-26

Change-Id: Ief3b586ff3d9f492f0277243b2a94952bab48786
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1156023
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-06-07 12:31:40 -07:00