Commit Graph

150 Commits

Author SHA1 Message Date
Terje Bergstrom
d29afd2c9e gpu: nvgpu: Fix signed comparison bugs
Fix small problems related to signed versus unsigned comparisons
throughout the driver. Bump up the warning level to prevent such
problems from occuring in future.

Change-Id: I8ff5efb419f664e8a2aedadd6515ae4d18502ae0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1252068
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2016-11-16 21:35:36 -08:00
Peter Daifuku
1ba169d7db Revert "Revert "gpu: nvgpu: vgpu: alloc hwpm ctxt buf on client""
This reverts commit 5f1c2bc27f.

Added back now that matching RM server has been updated:

In hypervisor mode, all GPU VA allocations must be done by client;
fix this for the allocation of the hwpm ctxt buffer

Bug 200231611

Change-Id: Ie5ce2c2562401b1f00821231d37608e3fc30d4a4
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1252138
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-11-14 15:04:22 -08:00
Terje Bergstrom
8fa5e7c58a gpu: nvgpu: Remove IOCTL FREE_OBJ_CTX
We have never used the IOCTL FREE_OBJ_CTX. Using it leads to context
being only partially available, and can lead to use-after-free.

Bug 1834225

Change-Id: I9d2b632ab79760f8186d02e0f35861b3a6aae649
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1250004
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2016-11-11 11:47:42 -08:00
Terje Bergstrom
d09d259d74 gpu: nvgpu: vgpu: Do not overwrite err code on fail
vgpu_vm_alloc_share() wants to return -EINVAL if VMA areas requested
do not fulfill the criteria. The error code gets overwritten by a
call to vgpu_comm_sendrecv(), which makes vgpu_vm_alloc_share() always
return 0.

Change-Id: I93f56025f963d1d4ad2f9b06139fce742d3be41b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249961
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
2016-11-11 08:20:31 -08:00
Terje Bergstrom
5855fe26cb gpu: nvgpu: Do not post events to unbound channels
Change-Id: Ia1157198aad248e12e94823eb9f273497c724b2c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1248366
Tested-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
GVS: Gerrit_Virtual_Submit
2016-11-07 15:47:49 -08:00
Sivaram Nair
5f1c2bc27f Revert "gpu: nvgpu: vgpu: alloc hwpm ctxt buf on client"
This reverts commit 57821e2157.

Change-Id: Ic4801115064ccbcd1435298a61871921d056b8ea
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/1247825
Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Babu Bodla <rbodla@nvidia.com>
2016-11-04 08:34:18 -07:00
Peter Daifuku
57821e2157 gpu: nvgpu: vgpu: alloc hwpm ctxt buf on client
In hypervisor mode, all GPU VA allocations must be done by client;
fix this for the allocation of the hwpm ctxt buffer

Bug 200231611

Change-Id: I0270b1298308383a969a47d0a859ed53c20594ef
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1240913
(cherry picked from commit 49314d42b13e27dc2f8c1e569a8c3e750173148d)
Reviewed-on: http://git-master/r/1245867
(cherry picked from commit d0b10e84d90d0fd61eca8be0f9e879d9cec71d3e)
Reviewed-on: http://git-master/r/1246700
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-11-03 10:35:12 -07:00
Alex Waterman
2fa54c94a6 gpu: nvgpu: Remove global debugfs variable
Remove a global debugfs variable and instead save the allocator
debugfs root node in the gk20a struct.

Bug 1799159

Change-Id: If4eed34fa24775e962001e34840b334658f2321c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1225611
(cherry picked from commit 1908fde10bb1fb60ce898ea329f5a441a3e4297a)
Reviewed-on: http://git-master/r/1242390
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-10-26 11:10:01 -07:00
Peter Daifuku
1b2529ba68 gpu: nvgpu: vgpu: css_vgpu: fix sparse warnings
css_vgpu.c: fix warnings found by sparse tool

Bug 200088648

Change-Id: I4d9d33c6438be8fa8f2ba9cb0b2f786c46b7c9ce
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1234605
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-10-12 13:02:12 -07:00
Aingara Paramakuru
3366506072 gpu: nvgpu: move gpfifo submit wait to userspace
Instead of blocking for gpfifo space in the nvgpu driver,
return -EAGAIN and allow userspace to decide the blocking
policy.

Bug 1795076

Change-Id: Ie091caa92aad3f68bc01a3456ad948e76883bc50
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/1202591
(cherry picked from commit 8056f422c6a34a4239fc4993c40c2e517c932714)
Reviewed-on: http://git-master/r/1203800
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-09-15 12:23:29 -07:00
Peter Daifuku
54e22a2bae gpu: nvgpu: vgpu: NULL out unused css entries
Fix cyclestats snapshots HAL entries in the vgpu case, need
to null out the ones that don't apply.

Bug 1700143
JIRA EVLR-278

Change-Id: I1b5f4652d1bf3283d96fdb3c2f66c4f69a9f6acc
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1217507
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
2016-09-13 11:34:03 -07:00
Peter Daifuku
9aa7de15c2 gpu: nvgpu: vgpu: cyclestat snapshot support
Add support for cyclestats snapshots in the virtual case

Bug 1700143
JIRA EVLR-278

Change-Id: I376a8804d57324f43eb16452d857a3b7bb0ecc90
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1211547
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-09-08 16:04:09 -07:00
Deepak Nibade
70cad5fbb5 gpu: nvgpu: unify nvgpu and pci probe
We have completely different versions of probe for
nvgpu and pci device
Extract out common steps into nvgpu_probe() function
and separate it out in new file nvgpu_common.c
Divide task of nvgpu_probe() into further smaller
functions

Do platform specific things (like irq handling,
memresource management, power management) only in
individual probes and then call nvgpu_probe() to
complete the common initialization

Move all debugfs initialization to common gk20a_debug_init()
This also helps to bringup all debug nodes to pci device

Pass debugfs_symlink name as a parameter to gk20a_debug_init()
This allows us to set separate debugfs symlink for nvgpu
and pci device

In case of railgating, cde and ce debugfs, check if
platform supports them or not

Copy vidmem_is_vidmem from platform to mm structure
and set it to true for pci device

Return from gk20a_scale_init() if we don't have either of
governor or qos_notifier

Fix gk20a_alloc_debugfs_init() and gk20a_secure_page_alloc()
to receive device pointer instead of platform_device

Export gk20a_railgating_debugfs_init() so that we can call
it from gk20a_debug_init()

Jira DNVGPU-56
Jira DNVGPU-58

Change-Id: I3cc048082b0a1e57415a9fb8bfb9eec0f0a280cd
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1204207
(cherry picked from commit add6bb0a3d5bd98131bbe6f62d4358d4d722b0fe)
Reviewed-on: http://git-master/r/1204462
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-09-08 09:43:51 -07:00
Alex Waterman
0e69c6707b gpu: nvgpu: Add gpu_dbg_map_v message type
Add a new debug message type: gpu_dbg_map_v. This is used for mapping
messages that are not specifically memory map operations.

Also cleanup the memory mapping debugging a bit since there was one
duplicate print and the memory map print was difficult to parse
visually. As a result the message has been modified to put the most
important information first in an easily readable format.

Bug 1732449
JIRA DNVGPU-12

Change-Id: Ib19c9371ee958009ab5a2d89b9610e699d070ee2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1198593
(cherry picked from commit 51dba53b06ca171cdb13d1707f2d026b0ce29f07)
Reviewed-on: http://git-master/r/1147670
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2016-08-30 10:04:23 -07:00
Thomas Fleury
fba43012c0 gpu: nvgpu: do not flush FECS record on engine reset
Flushing timestamp record method can fail in case FECS is not
processing the main method queue. In particular, this occurs
in case of ctxsw timeout, where we process fifo sched interrupts
from the host, but FECS is still waiting for idle (grWFI).
In such scenario, this adds huge delay in fifo recovery
procedure (timeout on FECS method). Since flushing the last
(incomplete) record from FECS would only be useful in that case
(context switch ongoing), remove flush operation on engine
reset. Note that an explicit ENGINE_RESET event (with pid)
is inserted in user-facing ctxsw buffer on engine reset.

Bug 200228310

Change-Id: I885525f8f197f81266b50db161bb511867fc74f4
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1207305
(cherry picked from commit 44391b6204fd648949295f90481b0c424d9a5ddf)
Reviewed-on: http://git-master/r/1208414
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-08-29 16:14:40 -07:00
Richard Zhao
06780e0681 gpu: nvgpu: vgpu: fix channel abort
set timeout for channel force reset, to prevent submit immediately.

Bug 1778448
JIRA VFND-2097

Change-Id: I729597a68cbdc5ed3f6c878955a10ae7c4659fa4
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1203298
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-08-23 11:13:00 -07:00
Richard Zhao
5d4319ad28 gpu: nvgpu: vgpu: add channel wdt support
- avoid dump gr registers for vgpu
- init wdt lock

Bug 1776876
JIRA VFND-2151

Change-Id: I73293e0d23b614129c763cb22b09156a8e1432cc
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1202256
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-08-18 15:03:56 -07:00
Richard Zhao
198b895a88 gpu: nvgpu: use force_reset_ch in ch wdt handler
- let force_reset_ch pass down err code
- force_reset_ch callback can cover vgpu too.

Bug 1776876
JIRA VFND-2151

Change-Id: I48f7890294c6455247198e0cab5f21f83f61f0e1
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1202255
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-08-18 15:03:54 -07:00
Richard Zhao
deffbf8ee2 gpu: nvgpu: vgpu: get constants of gpc_tpc_count/mask arrays
It'll cover multi-gpcs.

JIRA VFND-2103

Change-Id: Ie82bdaad360294696c5a679d694f6f0e2364ca2e
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1194631
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
2016-08-15 11:41:25 -07:00
Richard Zhao
ead3148816 gpu: nvgpu: vgpu: add getting gr constants
move below attributes to constants:
TEGRA_VGPU_ATTRIB_GPC_COUNT
TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT
TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT
TEGRA_VGPU_ATTRIB_NUM_FBPS
TEGRA_VGPU_ATTRIB_FBP_EN_MASK
TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP
TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC

JIRA VFND-2103

Change-Id: Ic2ac14a0f8a1cf19a996bcef20bef0003d3b9a3b
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1194630
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
2016-08-15 11:41:24 -07:00
Richard Zhao
843bbc726c gpu: nvgpu: vgpu: add getting sm version constants
move below attributes to constants:
TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH

JIRA VFND-2103

Change-Id: I5d6aa8f4a49e65307989ef02d223c3ee31fcdeed
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1190481
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
2016-08-15 11:41:23 -07:00
Richard Zhao
233862859a gpu: nvgpu: vgpu: add getting ltc constants
move below attributes to constants:
TEGRA_VGPU_ATTRIB_COMPTAG_LINES
TEGRA_VGPU_ATTRIB_L2_SIZE
TEGRA_VGPU_ATTRIB_CACHELINE_SIZE
TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE
TEGRA_VGPU_ATTRIB_SLICES_PER_LTC
TEGRA_VGPU_ATTRIB_LTC_COUNT

JIRA VFND-2103

Change-Id: Iecf9717ee553a16ffe8de445be5bfe5a99c3a094
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1190480
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
2016-08-15 11:41:21 -07:00
Richard Zhao
47fe8460e9 gpu: nvgpu: vgpu: add getting constants golden img size and zcull ctx size
JIRA VFND-2103

Change-Id: I180324b36a1c6b39300b92a2cff6448d7665679b
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1190479
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
2016-08-15 11:41:20 -07:00
Richard Zhao
9730a93d8a gpu: nvgpu: vgpu: add cmd to get RM server constants
Moving getting constant attributes into one cmd which will be
called only once.

This patch adds basic infrastructure and gpu arch info, max_freq
and num_channels support.

JIRA VFND-2103

Change-Id: I100599b49f29c99966f9e90ea381b1f3c09177a3
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1189832
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
2016-08-15 11:41:18 -07:00
Richard Zhao
e1438818b9 gpu: nvgpu: vgpu: add vgpu private data and helper functions
Move vgpu private data to a dedicated structure and allocate it
at probe time. Also add virt_handle helper function which is used
everywhere.

JIRA VFND-2103

Change-Id: I125911420be72ca9be948125d8357fa85d1d3afd
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1185206
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
2016-08-15 11:41:16 -07:00
Peter Daifuku
38a59acc77 gpu: nvgpu: move dbg_session_ops to gops
Move dbg_session_ops to gops for better code consistency

JIRA VFND-1905

Change-Id: I04a11d77dd8c26d9922e80e556822f80dd2bc36d
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1192641
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2016-07-30 11:29:20 -07:00
Alex Waterman
0793de62b2 gpu: nvgpu: Change the allocator flag naming scheme
Move to a more generic name of GPU_ALLOC_*.

Change-Id: Icbbd366847a9d74f83f578e4d9ea917a6e8ea3e2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1176445
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2016-07-19 11:31:50 -07:00
Alex Waterman
b6569319c7 gpu: nvgpu: Support multiple types of allocators
Support multiple types of allocation backends. Currently there is
only one allocator implementation available: a buddy allocator.
Buddy allocators have certain limitations though. For one the
allocator requires metadata to be allocated from the kernel's
system memory. This causes a given buddy allocation to potentially
sleep on a kmalloc() call.

This patch has been created so that a new backend can be created
which will avoid any dynamic system memory management routines
from being called.

Bug 1781897

Change-Id: I98d6c8402c049942f13fee69c6901a166f177f65
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1172115
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2016-07-19 11:21:46 -07:00
Thomas Fleury
f4b77e4656 gpu: nvgpu: process granularity for FECS traces
When processing FECS traces, a hash table is used
to retrieve the 'pid' of the process that created
the channel/TSG. Report process identifer (aka
tgid in kernel) instead of thread identifier (aka
pid) for FECS traces.

Bug 1736423

Change-Id: I54cb9d298b9fe3e1cccdd7145604cd01c5758c9d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1166501
(cherry picked from commit f7fd1f6d7ad0753b787ec20604a08a1f4882fe6f)
Reviewed-on: http://git-master/r/1168728
(cherry picked from commit 97a62e5b89352fce576f1bca71b38bf2242ff047)
Reviewed-on: http://git-master/r/1177823
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2016-07-18 23:19:09 -07:00
Thomas Fleury
c8ffe0fdec gpu: nvgpu: add sched control API
Added a dedicated device node to allow an
app manager to control TSG scheduling parameters:
- Get list of TSGs
- Get list of recent TSGs
- Get list of TSGs per pid
- Get TSG current scheduling parameters
- Set TSG timeslice
- Set TSG runlist interleave

Jira VFND-1586

Change-Id: I014c9d1534bce0eaea6c25ad114cf0cff317af79
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1160384
(cherry picked from commit 75ca739517cc7f7f76714b5f6a1a57c39b8cb38e)
Reviewed-on: http://git-master/r/1167021
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2016-07-18 23:12:51 -07:00
Richard Zhao
dc137541b0 gpu: nvgpu: vgpu: add pm qos support
Send cmd to RM server to change clk rate when PM_QOS_GPU_FREQ_BOUNDS
max changes.

Bug 200206160

Change-Id: I7f19e5f711426517baf8e7f934bf41972012644b
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1172792
(cherry picked from commit 973c258fd85449c3862df2498362e358fd3682c9)
Reviewed-on: http://git-master/r/1180892
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2016-07-13 21:46:07 -07:00
Konsta Holtta
d33fb5a964 gpu: nvgpu: use vidmem by default in gmmu_alloc variants
For devices that have vidmem available, use the vidmem allocator in
gk20a_gmmu_alloc{,attr,_map,_map_attr}. For others, use sysmem.

Because all of the buffers haven't been tested to work in vidmem yet,
rename calls to gk20a_gmmu_alloc{,attr,_map,_map_attr} to have _sys at
the end to declare explicitly that vidmem is used. Enabling vidmem for
each now is a matter of removing "_sys" from the function call.

Jira DNVGPU-18

Change-Id: Ibe42f67eff2c2b68c36582e978ace419dc815dc5
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1176805
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-07-08 04:19:04 -07:00
Deepak Nibade
e27c72446b gpu: nvgpu: simplify power management
We currenlty initialize both runtime PM and pm_domains frameworks
and use pm_domain to control runtime power management of NvGPU

But since GPU has a separate rail, using pm_domain is not
strictly required
Hence remove pm_domain support and use runtime PM only for all
the power management
This also simplifies the code a lot

Initialization in gk20a_pm_init()
- if railgate_delay is set, set autosuspend delay of runtime PM
- try enabling runtime PM
- if runtime PM is now enabled, keep GPU railgated
- if runtime PM is not enabled, keep GPU unrailgated
- if can_railgate = false, disable runtime PM and keep
  GPU unrailgated

Set gk20a_pm_ops with below callbacks for runtime PM
static const struct dev_pm_ops gk20a_pm_ops = {
.runtime_resume = gk20a_pm_runtime_resume,
.runtime_suspend = gk20a_pm_runtime_suspend,
.resume = gk20a_pm_resume,
.suspend = gk20a_pm_suspend,
}

Move gk20a_busy() to use runtime checks of pm_runtime_enabled()
instead of using compile time checks on CONFIG_PM

Clean up some pm_domain related code

Remove use of gk20a_pm_enable/disable_clk() since this
should be already done in platform specific unrailgate()/
railgate() APIs

Fix "railgate_delay" and "railgate_enable" sysfs to use
runtime PM calls

For VGPU, disable runtime PM during vgpu_pm_init()
With this, we will initialize vgpu with vgpu_pm_finalize_poweron()
upon first call to gk20a_busy()

Jira DNVGPU-57

Change-Id: I6013e33ae9bd28f35c25271af1239942a4fa0919
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1163216
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-07-08 00:58:53 -07:00
Peter Daifuku
1b04326f40 gpu: nvgpu: vgpu: dbg_set_powergate support
Add support for dbg_set_powergate when virtualized

Jira VFND-1905

Change-Id: I0d81c8863b3eda4ae4fee42e5a95d2fc9d78b174
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1162048
(cherry picked from commit 0dfc55f390a10e21ae13e14dd2f16e89a3bddfa7)
Reviewed-on: http://git-master/r/1167182
(cherry picked from commit 4e34a1844558d93da5ad208532ec28aeda228f95)
Reviewed-on: http://git-master/r/1174701
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
2016-07-06 15:26:22 -07:00
Konsta Holtta
b8915ab5aa gpu: nvgpu: support in-kernel vidmem mappings
Propagate the buffer aperture flag in gk20a_locked_gmmu_map up so that
buffers represented as a mem_desc and present in vidmem can be mapped to
gpu.

JIRA DNVGPU-18
JIRA DNVGPU-76

Change-Id: I46cf87e27229123016727339b9349d5e2c835b3e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1169308
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-07-06 03:34:23 -07:00
Shawn Joo
8fced97c65 gpu: nvgpu: vgpu: remove sysfs creation
gk20a sysfs is not currently applicable for vgpu.
Remove it for now.

Bug 200137760

Change-Id: Ia79eb5d0958856958fe74ce6eb6ccdd521a6f8f7
Signed-off-by: Shawn Joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/1164600
(cherry picked from commit 2a630b197df914244f5be0608598e395c3783664)
Reviewed-on: http://git-master/r/1172417
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-07-04 03:51:37 -07:00
Terje Bergstrom
475af509e1 gpu: nvgpu: vgpu: Add CE engine to engine list
Add CE engine to vgpu engine list. CE engine is defined differently
for different GPUs, so we also add HAL for initializing the engine
info.

Bug 1780185

Change-Id: I5ae265551feac08d0c4d45402dd3277514e62b2d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1169720
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Tested-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Lakshmanan M <lm@nvidia.com>
2016-06-24 09:10:39 -07:00
Richard Zhao
344d665119 gpu: nvgpu: vgpu: correct value of g->ltc_count
ltc.init_fs_state was not called for vgpu, because
vgpu has its own poweron function. fixed it.

Bug 1778448

Change-Id: I023625c3e2efc86e72e9dcd04195c5d0b3d0eada
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1165969
(cherry picked from commit 3304b459593e92650cb772301e9c5745abb6c371)
Reviewed-on: http://git-master/r/1169050
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-06-22 12:11:28 -07:00
Richard Zhao
da907c76e2 gpu: nvgpu: vgpu: disable batch map buffer in gpu characteristics
vgpu has not implemented batch map buffer yet, so report it in gpu
characteristics.

Bug 200201431

Change-Id: Ia9bfd71735889706242f0c06a1c44c5ed318ab6d
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1157467
(cherry picked from commit c6999995f9a48f645d6ffb6b7361d29cf641e5e3)
Reviewed-on: http://git-master/r/1156636
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-06-17 14:00:56 -07:00
Richard Zhao
22d0233d3a gpu: nvgpu: vgpu: add read ptimer support
Bug 1395833

Change-Id: Id0d427b6a1ddaecfeec33c61a6161679cf596c92
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1159588
(cherry picked from commit d33aa89420990626fb377c56ed5517a00f717c2a)
Reviewed-on: http://git-master/r/1158897
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-06-16 14:06:55 -07:00
Lakshmanan M
a295d90cac gpu: nvgpu: Add uapi support for non-graphics engines
Extend the existing NVGPU_GPU_IOCTL_OPEN_CHANNEL interface to allow
opening channels for other than the primary (i.e., the graphics)
runlists. This is required to push work to dGPU engines that have
their own runlists, such as the asynchronous copy engines and the
multimedia engines.

Minor change - Added active_engines_list allocation
and assignment for fifo_vgpu back end.

JIRA DNVGPU-25

Change-Id: I3ed377e2c9a2b4dd72e8256463510a62c64e7a8f
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1161541
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-06-13 07:45:19 -07:00
Richard Zhao
3735dba6f8 gpu: nvgpu: vgpu: add general event support
Events like bpt int/pause will help cuda work properly.

Bug 200173403
VFND-1568

Change-Id: I29e534969028bf08aedd81c99f5a536779f431d1
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1159621
(cherry picked from commit a266e53c514639e15ed166e2c8ce5a55efc48eda)
Reviewed-on: http://git-master/r/1152154
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-06-09 15:17:41 -07:00
Richard Zhao
c624f35383 gpu: nvgpu: vgpu: add channel enable support
Bug 200173403
VFND-1568

Change-Id: I3636a77bbbbd719e961dce5ca7ca7bdd5aa33881
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1159620
(cherry picked from commit b22fb6518da15a09c3e298213af5e60b8e6907a2)
Reviewed-on: http://git-master/r/1155403
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-06-09 15:17:28 -07:00
Sachit Kadle
e8b20c12cd gpu: nvgpu: vgpu: add channel force reset
Add forced channel reset support for vgpu

Bug 200187507
JIRA EVLR-337

Change-Id: I48e3e2b430f3a4ae94244225232902a8c037cb07
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1154781
(cherry picked from commit abd6688801fe76c822d6f67f554c18705d9f23d6)
Reviewed-on: http://git-master/r/1161259
GVS: Gerrit_Virtual_Submit
Tested-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-06-09 15:17:10 -07:00
Lakshmanan M
6299b00beb gpu: nvgpu: Add multiple engine and runlist support
This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt handling support
   for gm206 GPU family
5) Added generic mechanism to identify the
   CE engine pri_base address for gm206
   (CE0, CE1 and CE2)
6) Removed hard coded engine_id logic and
   made generic way
7) Code cleanup for readability

JIRA DNVGPU-26

Change-Id: I2c3846c40bcc8d10c2dfb225caa4105fc9123b65
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1155963
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-06-07 12:31:34 -07:00
Peter Daifuku
f48d28caa3 gpu: nvgpu: vgpu: add support for max_freq
Add vgpu support for max_freq characteristic

Bug 200182714
JIRASW VFND-1570

Change-Id: Ibeddfbba1bf0529d6f576cefcb82978dbae315d1
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1149216
(cherry picked from commit 8e8b5979e87268401d5b0fc658a73589710a2e09)
Reviewed-on: http://git-master/r/1155416
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-06-06 15:35:16 -07:00
Richard Zhao
b0ffd2f065 nvgpu: vgpu: add tsg set interleave support
added a new cmd to support setting tsg interleave level.

Bug 1702773
VFND-1492

Change-Id: Idd9b9c59180b156293ddfc4e2b879d0ea6908388
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1145024
(cherry picked from commit 0929ff1089fbc331b07e17073a46fda4086ae785)
Reviewed-on: http://git-master/r/1150706
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-05-31 10:48:10 -07:00
Richard Zhao
7a134457a8 gpu: nvgpu: vgpu: add tsg set timeslice support
Bug 1702773
JIRA VFND-1496

Change-Id: Ice570df78d974fa59f2a932caf0e6249b13493a1
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1144929
(cherry picked from commit 8b6ec996f3773e497a040a8fe4148e01e8dc35fa)
Reviewed-on: http://git-master/r/1150705
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-05-31 10:47:47 -07:00
Richard Zhao
d707c5a444 gpu: nvgpu: add tsg support for vgpu
- make tsg_gk20a.c call HAL for enable/disable channels
- add preempt_tsg HAL callbacks
- add tsg bind/unbind channel HAL callbacks
- add according tsg callbacks for vgpu

Bug 1702773
JIRA VFND-1003

Change-Id: I2cba74b3ebd3920ef09219a168e6433d9574dbe8
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1144932
(cherry picked from commit c3787de7d38651d46969348f5acae2ba86b31ec7)
Reviewed-on: http://git-master/r/1126942
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-05-31 10:47:22 -07:00
Richard Zhao
a71ce831fb gpu: nvgpu: vgpu: manage gr_ctx as independent resource
gr_ctx will managed as independent resource in RM server
and vgpu can get a gr_ctx handle.

Bug 1702773

Change-Id: I87251af61711f0d7997ce90df8a3de196a9b481a
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1144931
(cherry picked from commit 2efbd143adaf60570121f1c212dc6b6f3d5a1661)
Reviewed-on: http://git-master/r/1150704
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-05-31 10:46:33 -07:00