Commit Graph

12 Commits

Author SHA1 Message Date
Terje Bergstrom
e8bac374c0 gpu: nvgpu: Use device instead of platform_device
Use struct device instead of struct platform_device wherever
possible. This allows adding other bus types later.

Change-Id: I1657287a68d85a542cdbdd8a00d1902c3d6e00ed
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120466
2016-04-08 09:42:41 -07:00
Terje Bergstrom
4cc1457703 gpu: nvgpu: Move clk bypass div code to clk init
Clock bypass divider was changed just before resetting priv ring.
Move the code to a new clk op instead so that it is executed only on
gk20a.

Change-Id: Ic8084a4a5fac23770f50b50f910ced2543ba0f28
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/764970
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2015-07-03 07:51:42 -07:00
Alex Frid
30e47f6984 gpu: nvgpu: Combine delays with GK20A parameters
Specified locking timeout and IDDQ exit delay as GK20A PLL parameters,
and used this data instead of hard-coded numbers.

Change-Id: I59e16ed11fdba6911f2751195d182e68aed96851
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/735481
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2015-05-18 11:31:55 +05:30
Arun Kumar Swain
e5f82c848d arm: tegra: Register tegra-throttle cdev as driver
1. Register tegra-throttle cooling device as a
platform driver.
2. Obtain all the platform data (throtlle table
info) for all instances of blanced-throtlled cdev
from device tree and register them.

Change-Id: Ie92685eea3eb5cb18068b195adc9ab5f83762399
Signed-off-by: Arun Kumar Swain <arswain@nvidia.com>
Reviewed-on: http://git-master/r/449104
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
2015-03-18 12:10:43 -07:00
Alex Frid
44b9d5fdb0 gpu: nvgpu: Use GPU device name in clock get operation
Used GPU device name in clock get operation (instead of fixed name),
to make operation is common for GK20A and GM20B. Updated clock ids
in tegra clock framework accordingly.

Bug 1450787

Change-Id: Ifd5b9c3a6fd8db5b06e6dcd989285e8410794803
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/441711
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
2015-03-18 12:10:35 -07:00
Alex Frid
ea530792c4 gpu: nvgpu: Make clock operations static
Made GK20A and GM20B  clock operations static, since they are invoked
only via HAL interfaces.

Bug 1450787

Change-Id: Ia30218ad4244bd8790b5ef96d1963678d0ba39e1
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/441710
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
2015-03-18 12:10:35 -07:00
Hoang Pham
f7642ca185 gpu: nvgpu: Fork GM20B clock from GK20A clock
Bug 1450787

Change-Id: Id7fb699d9129a272286d6bc93e0e95844440a628
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/440536
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2015-03-18 12:10:33 -07:00
Alex Frid
b972f8d15e gpu: nvgpu: Init clock debugfs after clock support
Initialized GK20A clock debugfs after clock support
hardware and software are ready.

Bug 1450787

Change-Id: I8ec2ef303a84b9151b7ce209a1864f1729382a44
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/440973
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2015-03-18 12:10:33 -07:00
Alex Frid
d98099c9b6 gpu: nvgpu: Remove unused GK20A cooling device
Removed unused, obsolete GK20A cooling device.

Bug 1450787

Change-Id: I5b02546d0405dd518ec841d903e650a8d38db8f2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/437942
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2015-03-18 12:10:31 -07:00
Hoang Pham
ba387d3d7e gpu: Split clk_ops for GK20A and GM20B
Split clk_ops for GK20A and GM20B into different files

Bug 1450787

Change-Id: I34d16c54ac40c70854e80588475434c9e50b51a5
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/437771
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2015-03-18 12:10:29 -07:00
Alex Frid
3058fb2b96 gpu: nvgpu: Use 1kHz resolution for GPCPLL programming
Used 1kHz resolution (instead of 1 MHz) for GPCPLL programming:
limits specifications, calculating GPCPLL settings, storing target
frequency values, and proving output from debug monitor. Updated
comments in clock header to properly reflect frequency units.

Bug 1450787

Change-Id: Ica58f794b82522288f2883c40626d82dbd794902
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/437943
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2015-03-18 12:10:29 -07:00
Arto Merilainen
a9785995d5 gpu: nvgpu: Add NVIDIA GPU Driver
This patch moves the NVIDIA GPU driver to a new location.

Bug 1482562

Change-Id: I24293810b9d0f1504fd9be00135e21dad656ccb6
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/383722
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:08:53 -07:00