Commit Graph

9 Commits

Author SHA1 Message Date
Adeel Raza
eb63239f09 nvgpu: pmu: gv11b: add "U"s to _pginitseq_gv11b
MISRA Rule 7.2 Definition: A "u" or "U" suffix shall be applied to all
integer constants that are represented in an unsigned type.

To satisfy the requirements of this rule, a "U" suffix is added to all
the integer literals used for initializing the _pginitseq_gv11b array.

JIRA NVGPU-844

Change-Id: I6200936455117a6205bd282365d4bc90ee1ccccc
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990492
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2019-01-09 18:49:27 -08:00
Sai Nikhil
7ffbbdae6e gpu: nvgpu: MISRA Rule 7.2 misc fixes
MISRA Rule 7.2 Definition: A "u" or "U" suffix shall be applied to all
integer constants that are represented in an unsigned type.

This patch adds a "U" suffix to integer literals which are being
assigned to unsigned integer variables. In most cases the integer
literal is a hexadecimal value.

JIRA NVGPU-844

Change-Id: I8a68c4120681605261b11e5de00f7fc0773454e8
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959189
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2019-01-09 18:49:13 -08:00
Antony Clince Alex
b10960e7b7 gpu: nvgpu: Enable the reporting of ECC errors
Enable the reporting of ECC errors on hw modules
like gr, pmu and ltc. These errors will be notified
to the underlying safety service.

Jira NVGPU-1366

Change-Id: Ibf0f9761d30bcab31809f92aa2b4378360066385
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1955267
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Tested-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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2019-01-03 12:54:31 -08:00
Sai Nikhil
303fc7496c gpu: nvgpu: common: fix MISRA Rule 10.4 Violations
MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals or casting operands
to have same type of operands when an arithmetic operation is
performed.

This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.

JIRA NVGPU-992

Change-Id: I27e3e59c3559c377b4bd3cbcfced90fdf90350f2
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921459
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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2018-12-11 10:26:16 -08:00
Sagar Kamble
ac3cb4cc53 gpu: nvgpu: consolidate FALCON_ID macros
Same Falcon IDs were defined in acr_lsfm.h with additional
defines. Update definitions in falcon.h and remove from
acr_lsfm.h.

JIRA NVGPU-1459

Change-Id: Id08c7f7a16c36087984a4418ddf7f4921084971a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1964438
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2018-12-04 22:44:43 -08:00
Philip Elcan
e41ed1218e gpu: nvgpu: nix useless nvgpu_pmu_cmd_post param
The function nvgpu_pmu_cmd_post() included a timeout parameter, but all
callers were just passing the max value, so it was useless. This change
removes that parameter from that function. The same was true for
therm_pmu_cmd_post() that calls nvgpu_pmu_cmd_post(), so do the same to
it.

JIRA NVGPU-1008

Change-Id: I634ac40104ebd7cce36013a585dcb818aefd546a
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1962178
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2018-11-30 16:34:41 -08:00
Sagar Kamble
fd332ca6b4 gpu: nvgpu: s/*_flcn_*/*_falcon_*
There is mixed usage of falcon & flcn in function and data types.
Lets update all with "falcon" for consistency with file names.

JIRA NVGPU-1459

Change-Id: I02dbc866ce2cca009f2e8b87cfe11a919ec10749
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1953793
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2018-11-21 23:04:36 -08:00
Amulya
999eabbcd7 gpu: nvgpu: MISRA 10.1 boolean fixes
MISRA rule 10.1 doesn't allow the usage of non-boolean variables as
booleans.

Fix violations where a variable of type non-boolean is used as a
boolean and changed few instances of BIT() to BIT32() or BIT64().

JIRA NVGPU-646

Change-Id: I100606a69717c12839aa9c35e7bf6c18749db56e
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809836
GVS: Gerrit_Virtual_Submit
Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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2018-11-09 13:27:04 -08:00
Terje Bergstrom
f00d9ca1aa gpu: nvgpu: Move pmu HAL files to common/pmu
Move PMU and ACR HAL source code files to live under common/pmu. Also
update the #include paths and delete unnecessary #include dependencies.

JIRA NVGPU-961

Change-Id: I29a220bce6de0a46b6a5fe8ff7f9dc4d67395348
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1935626
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2018-11-08 20:04:06 -08:00