Commit Graph

5250 Commits

Author SHA1 Message Date
Seshendra Gadagottu
15860d77a4 gpu: nvgpu: fix compilation issues with PM disable
Fix gpu driver compilation issues with power mangement
and runtime power management disable.

Change-Id: I8e1873871d6f184013b2142dd0cbc32c67774177
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/417925
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:10 -07:00
Lauri Peltonen
f575bc6676 gpu: nvgpu: Support semaphore sync when aborting jobs
When aborting jobs on channel error situations, we manually set
the channel syncpoint's min == max in gk20a_disable_channel_no_update.
Nvhost will notice this manual syncpoint increment, and will call back
to gk20a_channel_update, which will clean up the job.

With semaphore synchronization, we don't have anybody calling back to
gk20a_channel_update, so we need to call it ourselves. Release job
semaphores (the equivalent of set_min_eq_max) on
gk20a_disable_channel_no_update, and if any semaphores were released,
call gk20a_channel_update afterwards.

Because we are actually calling gk20a_channel_update in some situations,
gk20a_disable_channel_no_update is no longer an appropriate name for the
function. Rename it to gk20a_channel_abort.

Bug 1450122

Change-Id: I1267b099a5778041cbc8e91b7184844812145b93
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/422161
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:10 -07:00
Lauri Peltonen
ae22cda010 gpu: nvgpu: Improve locking in semaphore_gk20a.c
Fix some possible race conditions when manipulating the mapping list of
semaphore pools.

Acquire a reference to the vm in gk20a_semaphore_pool_map, and release
that reference in gk20a_semaphore_pool_unmap.

Bug 1450122

Change-Id: I204e9c3dffd5162538b93e628d016dc06b3a5fb6
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/422160
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:10 -07:00
Lauri Peltonen
664ce15717 gpu: nvgpu: Destroy channel sync before releasing vm
The semaphore backend of gk20a_channel_sync uses the channel vm. We must
destroy the channel sync before freeing the channel vm.

Bug 1450122

Change-Id: I578567b7500672534d53facc58643df49df8b305
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/422159
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:10 -07:00
Lauri Peltonen
dbde063bf6 gpu: nvgpu: Update channel on semaphore release
When using semaphore based channel synchronization, a semaphore release
may mean that a job has completed. Call gk20a_channel_update from
gk20a_channel_semaphore_wakeup to check if there are memory refs to
release or sync timelines to signal.

Bug 1450122

Change-Id: Ib829c895dab05676c35f974d3f1c3d88c047c9b9
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/394576
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:10 -07:00
Lauri Peltonen
e204224b26 gpu: nvgpu: Add semaphore based gk20a_channel_sync
Add semaphore implementation of the gk20a_channel_sync interface.

Each channel has one semaphore pool, which is mapped as read-write to
the channel vm. We allocate one or two semaphores from the pool for each
submit.

The first semaphore is only needed if we need to wait for an opaque sync
fd. In that case, we allocate the semaphore, and ask GPU to wait for
it's value to become 1 (semaphore acquire method).  We also queue a
kernel work that waits on the fence fd, and subsequently releases the
semaphore (sets its value to 1) so that the command buffer can proceed.

The second semaphore is used on every submit, and is used for work
completion tracking. The GPU sets its value to 1 when the command buffer
has been processed.

The channel jobs need to hold references to both semaphores so that
their backing semaphore pool slots are not reused while the job is in
flight. Therefore gk20a_channel_fence will keep a reference to the
semaphore that it represents (channel fences are stored in the job
structure). This means that we must diligently close and dup the
gk20a_channel_fence objects to avoid leaking semaphores.

Bug 1450122
Bug 1445450

Change-Id: Ib61091a1b7632fa36efe0289011040ef7c4ae8f8
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/374844
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:08 -07:00
Allen Yu
4d278fdfd7 gpu: nvgpu: Turn on scaling when powered
This patch reorders scaling resume to happen always when
we power on the GPU, so as to balance the scaling suspend
when we power off GPU.

bug 200010911

Change-Id: I9fde817fbf9fed7d90c48ea06050db4b82e670a8
Signed-off-by: Allen Yu <alleny@nvidia.com>
Reviewed-on: http://git-master/r/421541
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2015-03-18 12:10:07 -07:00
Terje Bergstrom
131bcbcea9 gpu: nvgpu: Do not warn about unknown ctxsw region
Do not warn about unknown regions in ctxsw firmware blob.

Bug 1435870

Change-Id: I343d85a09a3cd1d7c1c881836af6868296409f07
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/420670
2015-03-18 12:10:06 -07:00
Terje Bergstrom
f551891483 gpu: nvgpu: Add rail gating trace events
Change-Id: I661f14b2858fb7bc993157a597d4a278859da837
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/418789
Reviewed-by: Automatic_Commit_Validation_User
2015-03-18 12:10:06 -07:00
Deepak Nibade
614b804159 gpu: nvgpu: print intr code for class error
Print interrupt code and channel id for unhandled gr class error.

Bug 200010403

Change-Id: Iedceaf4b8b6363b26f1836256875fb9b5c43eded
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/419566
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:06 -07:00
Deepak Nibade
3f8d5536a0 gpu: nvgpu: add accessor for gr_class_error
Add accessors to read class error code from
NV_PGRAPH_CLASS_ERROR

Bug 200010403

Change-Id: Ia99f50e264f9b8aa93f99994e52424418a2e4f74
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/419565
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:06 -07:00
Deepak Nibade
ccbe6c44d3 gpu: nvgpu: fix memory leak of dbg_session
In gk20a_dbg_gpu_dev_release() (when we close nvhost-dgb-gpu sysfs),
we return from function if there is no channel bound to dbg_session
without freeing the dbg_session memory.

If there is no channel bound then do not call dbg_unbind_channel_gk20a()
and then free dbg_session memory always.

Bug 200010382

Change-Id: I90dd2ed3cd72fbc5d429799660daf2a09b974fda
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/419306
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:05 -07:00
Terje Bergstrom
6b33379c55 gpu: nvgpu: Rewrite PMU boot-up sequence
Rewrite PMU boot sequence as a state machine. At PMU power-up send
initial messages, and reset state machine. At each reply from PMU,
do the next stage of PMU boot and set state.

As now PMU and FECS boot are independent, we need to ensure engine
idle before saving ZBC.

Change-Id: I1ea747ab794ef08f1784eeabfdae7655d585ff21
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/410205
2015-03-18 12:10:05 -07:00
Terje Bergstrom
cd13ee4aaf gpu: nvgpu: Set ch error before channel disable
In error case we first disabled the channel, and reset sync point to
max. After this we set channel error state. This causes a race if
channel is closed between setting sync point and setting channel
state.

Rearrange the code so that error state is set first, and only then
channel is disabled.

Bug 1519646

Change-Id: I20550f6a2708f892b6ba4ee714e90bdecdd128ad
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/418948
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
2015-03-18 12:10:05 -07:00
Terje Bergstrom
f2e30622a1 gpu: nvgpu: Reload ZBC values on rail gate exit
When exiting rail gate, we reloaded default ZBC values. The correct
behavior is to reload the values.

Bug 1447255

Change-Id: I7aad3586dda91a91a3629062a27001af281b955e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/418346
2015-03-18 12:10:04 -07:00
Terje Bergstrom
6446496902 gpu: nvgpu: On FECS error, dump ARB status
On FECS arbiter timeout, dump ARB status.

Change-Id: I4f8c4d38c99e35ce751172a8695e950f0ce594c8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/417753
2015-03-18 12:10:04 -07:00
Seshendra Gadagottu
4e9030f34d gpu: nvgpu: update gpmu supported versions
Updated gmpu ucode versions supported for gm20b.
Bug 1514021

Change-Id: If9cbde60449f5cc2b9c39c36ab5c79985d320bf8
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/418479
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:04 -07:00
Kevin Huang
7d917f43a5 gpu: nvgpu: gm20b: fix compression sharing
For GM20B alone, the LTC count is already accounted for the HW logic
for the CBC base calculation from the postDivide address. So SW
doesn't have to explicity divide it by the LTC count in the postDivide
address calculation.

Bug 1477079

Change-Id: I558bbe66bbcfb7edfa21210d0dc22c6170149260
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/414264
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:03 -07:00
Terje Bergstrom
28c35a1b99 gpu: nvgpu: Fault engines on PBDMA error
On PBDMA error even though the engine might not be wedged, we need to
kick the channel out of engine. Add that logic. Also when channel is
not in engine, we need to remove it from runlist.

Bug 1498688

Change-Id: I5939feb41d0a90635ba313b265c7e3b5d3f48622
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/417682
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2015-03-18 12:10:03 -07:00
Terje Bergstrom
bcf8c6411c gpu: nvgpu: Remove extraneous FB flush calls
gk20a_mm_fb_flush() invoked G_ELPG_FLUSH and FB_FLUSH. Remove the
invokation of G_ELPG_FLUSH. Replace calls to gk20a_mm_fb_flush() with
gk20a_mm_l2_flush() when appropriate.

Bug 1421824

Change-Id: I02af4bdc3b7bd26d0f6a8d610f70349269775a36
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/408210
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
2015-03-18 12:10:03 -07:00
Seshendra Gadagottu
846f0c4f41 gpu: nvgpu: select NETA for gm20b
Bug 1514021
Change-Id: I5bf942245a42881a418eb9e18c148287b6901ca0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/415531
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
2015-03-18 12:10:03 -07:00
Dan Willemsen
7e470c49a6 gpu: nvgpu: Create trace events last
Otherwise other trace event headers included may also be created, which
leads to duplicate definition issues in the 3.14 kernel.

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
2015-03-18 12:10:01 -07:00
Kevin Huang
18939e4b4a gpu: nvgpu: add support to Maxwell sparse texture
Bug 1442531

Change-Id: Ie927cca905b2ea9811417e7a1fdfdf9d48f015e2
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
2015-03-18 12:09:59 -07:00
Kevin Huang
da56b17de0 gpu: nvgpu: add generic api for sparse memory
Bug 1442531

Change-Id: I97408b54e27f5ed6411792e73f079a6f86cbe5f6
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
2015-03-18 12:09:59 -07:00
Kirill Artamonov
d364553f7c gpu: nvgpu: implement mapping for sparse allocation
Implement support for partial buffer mappings.

Whitelist gr_pri_bes_crop_hww_esr accessed by
fec during sparse texture initialization.

bug 1456562
bug 1369014
bug 1361532

Change-Id: Ib0d1ec6438257ac14b40c8466b37856b67e7e34d
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/375012
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:59 -07:00
Terje Bergstrom
5dc7fd0243 gpu: nvgpu: Handle PBDMA errors
Add handling for PBDMA errors.

Bug 1498688

Change-Id: Iff391110db1c270c05c76e6a14b7c666da8e3751
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:59 -07:00
Deepak Nibade
2ad53bb4ca gpu: nvgpu: add is_railgated() callback
Add is_railgated() platform callback to check status
of gk20a power rail

Bug 1376916
Bug 1487804

Change-Id: Ia0d909210dc409ab684eb6f20528b81500aecd5c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
2015-03-18 12:09:58 -07:00
Deepak Nibade
cd9f8553ad gpu: nvgpu: sysfs to put gpu into idle
- Add a sysfs "force_idle" to forcibly idle the GPU
- read on this sysfs will return the current status

0 : not in idle (running)
1 : in forced idle state

"echo 1 > force_idle" will force the gpu into idle
"echo 0 > force_idle" will cause the gpu to resume

Bug 1376916
Bug 1487804

Change-Id: I48dfd52e0d14561220bc4baea0776d1bdfaa7ea5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
2015-03-18 12:09:58 -07:00
Deepak Nibade
3f7be93dab gpu: nvgpu: add railgate check in do_idle()
In gk20a_do_idle(), check gk20a rail status before returning.
If rail is off, then only return success otherwise return
failure

Bug 1376916
Bug 1487804

Change-Id: I6280bf06c686b8baa4d6f49e90f47148411c3e02
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/415281
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:58 -07:00
Lauri Peltonen
954117fe11 gpu: nvgpu: Support sync framework with semaphores
Add sync_gk20a.c/h that support creating Android sync fence fd's from
gk20a semaphores.

Bug 1445450

Change-Id: I42272996721ceec38ba5510eae6770720bc9dd10
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/374843
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:57 -07:00
Terje Bergstrom
1c9aaa1eaf gpu: nvgpu: Implement ELPG flush for gm20b
ELPG flush is initiated from a common broadcast register, but must be
waited on via per-L2 registers. Split gk20a and gm20b versions of
the flush.

Change-Id: I75c2d65e8da311b50d35bee70308b60464ec2d4d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/401545
Reviewed-by: Automatic_Commit_Validation_User
2015-03-18 12:09:57 -07:00
Terje Bergstrom
24fc5e36a7 gpu: nvgpu: Initialize FECS explicitly on recovery
Instead of calling second phase of PMU boot sequence, initialize FECS
directly.

Change-Id: I7f9de0c5ec42049033839d244979f3f3daabf317
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/410204
2015-03-18 12:09:56 -07:00
Terje Bergstrom
48f0b407f9 gpu: nvgpu: Add gm20b fecs/gpccs bootloader support
Add support for booting FECS and GPCCS via faster bootloader method.
We leave this disabled until the bootloader binaries are checked in.

Change-Id: I39df5d116f7a33486407518c743638b01923970d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/413005
2015-03-18 12:09:56 -07:00
Terje Bergstrom
d78dca61e0 gpu: nvgpu: Remove deferred ELPG enable
Prevent the disable ELPG routine from calling deferred re enablement of
ELPG. Remove code related to deferred ELPG enable..

Change-Id: I9401e6e0f26a4e332e50eb38439e2ef6fcb4225d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/410203
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
2015-03-18 12:09:54 -07:00
Terje Bergstrom
c079c38d75 gpu: nvgpu: Add PMU sent/recvd messages to dbg log
Add debug log entries for received and sent PMU messages.

Change-Id: I94cecca76257d74785c13f1c5f97a7233361019f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/410202
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
2015-03-18 12:09:54 -07:00
Deepak Nibade
ab386e54a5 gpu: nvgpu: gk20a: add do_{idle()/unidle()} APIs
Add below two new APIs for gk20a :

1) gk20a_do_idle()
this API will force GPU to idle and railgate

2) gk20a_do_unidle()
this API will unblock all the tasks blocked by do_idle()

Bug 1487804

Change-Id: Ic5e7f2d19fb8d35f43666d0e309dde3022349d92
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/412061
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:53 -07:00
Deepak Nibade
6eab11c6e8 gpu: nvgpu: gk20a: add busy lock
- add rw_semaphore busy_lock for gpu busy() path
- take read lock on busy_lock inside gk20a_busy()
  so that all usual requests can execute simultaneously
- write lock can be taken when we need to block all
  of the gk20a_busy() calls

Bug 1487804

Change-Id: I1b162b38bce9621723d3e45280c6076816cf771a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/412060
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:53 -07:00
Deepak Nibade
77a0b8eb13 gpu: nvgpu: gk20a: export wait_channel_idle()
- Export gk20a_wait_channel_idle() function from channel_gk20a.h
- also, return error -EBUSY from this function when channel is
  found to be not idle

Bug 1487804

Change-Id: Ia7425e9b1332260ee9a53dca55ab07541f2755a9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/412059
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:53 -07:00
Terje Bergstrom
0d7533fb4f gpu: nvgpu: When rail gating, flush only once
When rail gating invoke G_ELPG_FLUSH only once.

Bug 1421824

Change-Id: Ibde0e32b212e3b030e69a9cb837c87789887aabb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/408209
2015-03-18 12:09:53 -07:00
Terje Bergstrom
2fbf6e7afb gpu: nvgpu: Allow suppressing WFI on submit
Allow suppressing WFI when submitting work and requesting a fence
back.

Bug 1491545

Change-Id: Ic3d061bb4f116cf7ea68dbd6a1b2ace9f11d0ab5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/390457
2015-03-18 12:09:53 -07:00
Terje Bergstrom
af8c1dc3a8 gpu: nvgpu: Use old ctxsw boot method on gm20b
Boot FECS/GPCCS with old method on gm20b. We don't yet have
bootloader for it.

Change-Id: I09046960cd86b0402d3ea2cd8e4c92597766fa10
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/412604
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2015-03-18 12:09:52 -07:00
Lauri Peltonen
e6b3d1e87f gpu: nvgpu: Add gk20a semaphore APIs
Add semaphore_gk20a.c/h that implement a new semaphore management API
for the gk20a driver. The API introduces two entities, 'semaphore pools'
and 'semaphores'.

Semaphore pools are memory areas dedicated for hosting one or more
semaphores. Typically, one pool equals one 4K page. A semaphore pool
is always mapped to the kernel memory, and it can be mapped and
unmapped to gpu address spaces using gk20a_semaphore_pool_map/unmap.

Semaphores are backed by 16 bytes of memory allocated from a semaphore
pool. The value of a semaphore can be 0=acuired or 1=released. When
allocated, the semaphores are initialized to the acquired state. They
can be released, or their releasing can be waited for by the CPU or GPU.

Semaphores are intended to be used only once, and after they are
released they should be freed so that the slot within the semaphore
pool can be reused. However GPU jobs must take references to the
semaphores that they use (similarly as they take references on memory
buffers that they use) so that the semaphore backing memory is not
reused too soon.

Bug 1450122
Bug 1445450

Change-Id: I3fd35f34ca55035decc3e06a9c0ede20c1d48db9
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/374842
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:52 -07:00
Deepak Nibade
dadaa5af56 gpu: nvgpu: gk20a: fix syncpt names for gk20a
nvhost_get_syncpt_host_managed() creates syncpt name based on
platform_device pointer passed to it
Passing host1x's pointer to this API results in setting gk20a
syncpt names as "host1x_0" which is conflicting

Hence to restore this pass gk20a's device pointer
which gives syncpt names as "gk20a.0_0"

Also, add a syncpt check for sycnpt received.

Bug 1305024

Change-Id: I4ff96c7c9ebff2dca385c5787a85b4a9451b9514
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/410121
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:51 -07:00
Terje Bergstrom
48239f5f8c gpu: nvgpu: Prune redundant cache maintenance
Remove redundant cache maintenance operations. Instance blocks and
graphics context buffers are uncached, so they do not need any cache
maintenance.

Bug 1421824

Change-Id: Ie0be67bf0be493d9ec9e6f8226f2f9359cba9f54
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/406948
2015-03-18 12:09:49 -07:00
Terje Bergstrom
3e5c123862 gpu: nvgpu: Always initialize system vm
PMU, FECS and GPCCS use the same address space. We used to initialize
the address space only if PMU is enabled. Create the system address
space always.

FECS and GPCCS used to have slower bit bang and faster DMA method
for loading ucode. Slower method is needed when FECS and GPCCS do not
have an address space. Remove the slower method as not anymore
needed.

Change-Id: I155619741ecc36aa6bf13a9c1ccb03c7c1330f0a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/406771
2015-03-18 12:09:49 -07:00
Deepak Nibade
df1852752a gpu: nvgpu: gk20a: free syncpt if last submit is complete
In channel_update(), we detect if channel is idle and if it is
idle then we free the syncpt. We do not free the syncpt if WFI is
scheduled on some other path.

Instead of checking for WFI, we can check if last submit is complete
or not (it can be WFI as well) and if last submit is complete then
we can free the syncpt.

Locking mechanism using submit lock will take care that syncpt is
kept alive until last submit or WFI completes

Bug 1305024

Change-Id: Ieafb82e1f924a01236ca73ed151eb03e88729835
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/405201
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:49 -07:00
Terje Bergstrom
2b48263b1f gpu: nvgpu: Do not realloc perfmon sample buffer
Allocate perfmon sample buffer only once.

Bug 1512840

Change-Id: I3f2a62b0fa28e6ba984ae3068a1d56ba461a0c29
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/408180
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>
2015-03-18 12:09:49 -07:00
Terje Bergstrom
66bb831f44 gpu: nvgpu: Register as subdomain of host1x
Add gk20a as a sub power domain of host1x. This enforces keeping
host1x on when using gk20a.

Bug 200003112

Change-Id: I08db595bc7b819d86d33fb98af0d8fb4de369463
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/407006
(cherry picked from commit 009812b3e510518740e9c7e89b8b8b80439fe26a)
Reviewed-on: http://git-master/r/408013
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:48 -07:00
Kevin Huang
69f5a5718b gpu: nvgpu: gm20b: add ltc isr
Bug 1507804

Change-Id: Ic58e21f4d995cf4f4fc7bb5fc6ec84a6c4d25d46
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/403214
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:48 -07:00
Kevin Huang
0781b55fc1 gpu: nvgpu: halize ltc isr
Bug 1507804

Change-Id: I3cca0e83dbf911c94422f8bb0b2df675a170b990
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/403213
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:48 -07:00