3 Commits

Author	SHA1	Message	Date
Konsta Holtta	cd4b2f642c	gpu: nvgpu: add HAL for reading ccsr_channel ... Refactor read accesses to the ccsr_channel register for channel state to be done via a channel HAL op for all chips. A new op called read_state is added for this; information needed by other units is collected in a new struct nvgpu_channel_hw_state. Jira NVGPU-1307 Change-Id: Iff9385c08e17ac086d97f5771a54b56b2727e3c4 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017266 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-02-12 17:06:09 -08:00
Konsta Holtta	7189630e7c	gpu: nvgpu: drop fifo_ in channel HAL names ... Now that the moved HAL ops from fifo are in channel, rename the implementations to match. Jira NVGPU-1307 Change-Id: I7b9336f506c9e71bcd0af98886216958bd6695eb Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017264 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-02-12 17:05:56 -08:00
Konsta Holtta	5cde4c2140	gpu: nvgpu: move chip specific channel reg ops to common ... Extract out the HAL ops' implementation that now belongs to the channel unit. This unit is responsible for channel register accesses and the like (ccsr_*). Rename channel_gm20b_bind to gm20b_fifo_channel_bind to match with the rest of the naming. Same with channel_gv11b_unbind. Jira NVGPU-1307 Change-Id: I58b9d96dbdaf36bdb163a5729544a41faec828ab Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017262 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-02-12 17:05:43 -08:00