4 Commits

Author	SHA1	Message	Date
Mahantesh Kumbar	4bb9b0b987	gpu: nvgpu: use support_ls_pmu flag to check LS PMU support ... Currently PMU support enable check is done with multiple methods which added complexity to know status of PMU support. Changed to replace multiple methods with support_pmu flag to know the PMU support, support_pmu will be updated at init stage based on platform/chip specific settings to know the PMU support status. Cleaned up support_pmu flag check with platform specific PMU members in multiple places & moved check to public functions JIRA NVGPU-173 Change-Id: Ief2c64250d1f78e3b054203be56499e4d1d9b046 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2024024 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-04 03:33:16 -08:00
Philip Elcan	f6c012b39d	gpu: nvgpu: lpwr: fix MISRA 10.3 violations ... MISRA Rule 10.3 prohibits implicit assignments of objects to different size or essential type. This fixes a number of these issues in common/pmu/lpwr. JIRA NVGPU-1008 Change-Id: Ia9cc0609f8c923cff38c9f85c2920aa60a522923 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2017605 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-02-21 00:15:43 -08:00
Divya Singhatwaria	068341d27c	gpu: nvgpu: Fix MISRA 16.1 violations ... Rule 16.1 states that all switch statements shall be well-formed: - Every switch-clause will have default case. - The switch-clause will end with an unconditional break statement. - The switch statement will have two or more conforming switch clauses. JIRA NVGPU-1509 Change-Id: I17ec54ba082d4a0e4464d9d4c4084d60e498f1a1 Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1979627 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-01-22 03:04:11 -08:00
Terje Bergstrom	dce78f7332	gpu: nvgpu: Move PMU code to common/pmu ... Move code interfacing with PMU tasks to common/pmu. JIRA NVGPU-961 Change-Id: Ie62611b0ffe1196d4bfdc740e03017e1894a834f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1950991 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-01-10 20:09:55 -08:00