nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: lpwr: fix MISRA 10.3 violations

Browse Source 
MISRA Rule 10.3 prohibits implicit assignments of objects to different
size or essential type. This fixes a number of these issues in
common/pmu/lpwr.

JIRA NVGPU-1008

Change-Id: Ia9cc0609f8c923cff38c9f85c2920aa60a522923
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017605
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-02-04 15:51:17 -05:00
committed by mobile promotions
parent dc9ba05cd4
commit f6c012b39d
4 changed files with 21 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -235,7 +235,8 @@ static void nvgpu_pmu_handle_param_lpwr_msg(struct gk20a *g,
int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
{
struct pmu_cmd cmd;
u32 seq, status = 0;
u32 seq;
int status = 0;
u32 payload = NV_PMU_PG_PARAM_MCLK_CHANGE_MS_SWASR_ENABLED;
struct clk_set_info *pstate_info;
u32 ack_status = 0;
@@ -255,11 +256,13 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
}
if (payload != g->perf_pmu->lpwr.mclk_change_cache) {
size_t tmp_size = PMU_CMD_HDR_SIZE +
sizeof(struct pmu_pg_cmd_mclk_change);
g->perf_pmu->lpwr.mclk_change_cache = payload;
cmd.hdr.unit_id = PMU_UNIT_PG;
cmd.hdr.size = PMU_CMD_HDR_SIZE +
sizeof(struct pmu_pg_cmd_mclk_change);
nvgpu_assert(tmp_size <= U8_MAX);
cmd.hdr.size = (u8)(tmp_size);
cmd.cmd.pg.mclk_change.cmd_type =
PMU_PG_CMD_ID_PG_PARAM;
cmd.cmd.pg.mclk_change.cmd_id =
@@ -282,17 +285,20 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
return status;
}
u32 nvgpu_lpwr_post_init(struct gk20a *g)
int nvgpu_lpwr_post_init(struct gk20a *g)
{
struct pmu_cmd cmd;
u32 seq;
u32 status = 0;
int status = 0;
u32 ack_status = 0;
size_t tmp_size = PMU_CMD_HDR_SIZE +
sizeof(struct pmu_pg_cmd_post_init_param);
(void) memset(&cmd, 0, sizeof(struct pmu_cmd));
cmd.hdr.unit_id = PMU_UNIT_PG;
cmd.hdr.size = PMU_CMD_HDR_SIZE +
sizeof(struct pmu_pg_cmd_post_init_param);
nvgpu_assert(tmp_size <= U8_MAX);
cmd.hdr.size = (u8)tmp_size;
cmd.cmd.pg.post_init.cmd_type =
PMU_PG_CMD_ID_PG_PARAM;
@@ -364,7 +370,7 @@ bool nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num)
int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock)
{
struct nvgpu_pmu *pmu = &g->pmu;
u32 status = 0;
int status = 0;
bool is_mscg_supported = false;
bool is_rppg_supported = false;
u32 present_pstate = 0;

6
drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c
View File

@@ -24,6 +24,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/pmu/pstate.h>
#include <nvgpu/pmu/lpwr.h>
#include <nvgpu/bug.h>
#include "gp106/bios_gp106.h"
@@ -54,11 +55,12 @@ static int rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd)
u32 seq;
int status = 0;
u32 success = 0;
size_t tmp_size = PMU_CMD_HDR_SIZE + sizeof(struct nv_pmu_rppg_cmd);
(void) memset(&cmd, 0, sizeof(struct pmu_cmd));
cmd.hdr.unit_id = PMU_UNIT_PG;
cmd.hdr.size = PMU_CMD_HDR_SIZE +
sizeof(struct nv_pmu_rppg_cmd);
nvgpu_assert(tmp_size <= U8_MAX);
cmd.hdr.size = (u8)tmp_size;
cmd.cmd.pg.rppg_cmd.cmn.cmd_type = PMU_PMU_PG_CMD_ID_RPPG;
cmd.cmd.pg.rppg_cmd.cmn.cmd_id = prppg_cmd->cmn.cmd_id;

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1232,7 +1232,7 @@ struct gpu_ops {
u32 feature_id);
int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock);
int (*pmu_lpwr_disable_pg)(struct gk20a *g, bool pstate_lock);
u32 (*pmu_pg_param_post_init)(struct gk20a *g);
int (*pmu_pg_param_post_init)(struct gk20a *g);
void (*dump_secure_fuses)(struct gk20a *g);
int (*reset_engine)(struct gk20a *g, bool do_reset);
bool (*is_engine_in_reset)(struct gk20a *g);

2
drivers/gpu/nvgpu/include/nvgpu/pmu/lpwr.h
View File

@@ -96,7 +96,7 @@ int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock);
int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock);
bool nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num);
bool nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num);
u32 nvgpu_lpwr_post_init(struct gk20a *g);
int nvgpu_lpwr_post_init(struct gk20a *g);
int init_rppg(struct gk20a *g);