Some of the engine queue related defines are shared by PMU, SEC2 and
queue implementations and currently in gpmuif_cmn.h. Let us add
engine_queue.h header file to club all those defines together.
JIRA NVGPU-1994
Change-Id: I57a889e6d14d954d2660e513994bb87cbb1e5824
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019414
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
engine queue head and tail methods were retrieved from falcon structure.
engine queue initialization can get these methods directly from hal
through params. Also eliminate struct nvgpu_falcon dereference in engine
queue sources to remove inclusion of falcon_priv.h.
JIRA NVGPU-1994
Change-Id: Idbebd5049cfd14eb3fe0e27b2bef8436cc61e101
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016290
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
As we plan to move the queue implementations out of falcon unit let us
rename these as:
1. engine_mem_queue - Generic implementation.
2. engine_dmem_queue - DMEM queue implementation of engine_mem_queue.
3. engine_emem_queue - EMEM queue implementation of engine_mem_queu.
4. engine_fb_queue - FB queue implementation.
JIRA NVGPU-1994
Change-Id: Ic81dcc154b3383d9f75fe57cc01269bda2698b25
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016288
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
FB queues handling is different from DMEM/EMEM queues in many aspects.
For e.g. no rewind required, additional queue struct fields, additional
queue operations required only for FB queues, push/pop semantics are
different.
Hence prepare separate structure and APIs for FB queues. PMU will have
to deal with the queue implementation chosen. This patch does the follo-
wing:
1. Update function/structure names to falcon_fb_queue_<op/name>.
2. Export nvgpu_falcon_fb_queue_* structure and functions.
3. Removed rewind function pointer and used direct functions for push,
pop and has_room.
4. PMU wrapper defined to use appropriate queue for empty check -
nvgpu_pmu_queue_is_empty.
5. PMU side updates for handling the work buffer and SEC2 updates for
usage of public queue functions.
JIRA NVGPU-1994
Change-Id: Ia5e40384e6e3f9e81d5dbc3d8138eb091337c086
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016285
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA rule 10.1 mandates that the correct data types are used as
operands of operators. For example, only unsigned integers can be used
as operands of bitwise operators.
This patch fixes rule 10.1 vioaltions for drivers/gpu/nvgpu/common.
JIRA NVGPU-777
JIRA NVGPU-1006
Change-Id: I53fe750f1b41816a183c595e5beb7bd263c27725
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971221
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
With intention to make falcon header free of private data we are making
all falcon struct members (pmu.flcn, sec2.flcn, fecs_flcn, gpccs_flcn,
nvdec_flcn, minion_flcn, gsp_flcn) in the gk20a, pointers to struct
nvgpu_falcon. Falcon structures are allocated/deallocated by
falcon_sw_init & _free respectively.
While at it, remove duplicate gk20a.pmu_flcn and gk20a.sec2_flcn,
refactor flcn_id assignment and introduce falcon_hal_sw_free.
JIRA NVGPU-1594
Change-Id: I222086cf28215ea8ecf9a6166284d5cc506bb0c5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968242
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
pmu.g & sec2.g were set in nvgpu_falcon_sw_init. They are now set
in nvgpu_early_init_pmu_sw & nvgpu_init_sec2_setup_sw. Pass gk20a
& pmu struct to nvgpu_init_pmu_fw_support like sec2.
pmu_fw_support & sec2_setup_sw are separated from respective init
sequence and now are called earlier since we need ->g member earlier
and most of the setup is sw only.
nvgpu_init_pmu_fw_ver_ops is now being exported.
JIRA NVGPU-1594
Change-Id: I6c71c6730ce06dad190159269e2cc60301f0237b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968241
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA Rule 10.1 states that operands shall not be of an
inappropriate essential type.
For example, the use of bitwise OR on signed values is not
permitted.
Both the pmu_read_message() and sec2_read_message() routines
do this in some cases when an error (or unexpected number of
bytes) is returned from the falcon queue pop/rewind routines.
This patch eliminates the MISRA violations by modifying these
cases to return the falcon queue operation error unmodified in the
corresponding status argument (or use -EINVAL in the event the
requested number of bytes isn't returned).
To reduce code duplication new pmu_falcon_queue_read() and
sec2_falcon_queue_read() routines are added here to wrap the
code that handles the error for the respective units.
Note that higher up in the call sequence (tu104_sec2_isr() in the
sec2_read_message() case and gk20a_pmu_isr() in the pmu_read_message()
case) the actual status value is only checked for non-zero or ignored
altogether. So it appears no existing code would depend on the
bitwise OR result anyway.
JIRA NVGPU-650
Change-Id: Id303523ac096f1989e612044082e0a62ae8179c2
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972624
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals or casting operands
to have same type of operands when an arithmetic operation is
performed.
This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: I27e3e59c3559c377b4bd3cbcfced90fdf90350f2
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921459
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.
Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.
JIRA NVGPU-1022
Change-Id: I957f8ca1fa0eb00928c476960da1e6e420781c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941002
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA Rule-15.6 requires that all if-else blocks and loop blocks
be enclosed in braces, including single statement blocks. Fix errors
due to single statement if-else and loop blocks without braces
by introducing the braces.
JIRA NVGPU-775
Change-Id: Ib70621d39735abae3fd2eb7ccf77f36125e2d7b7
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928745
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in common code.
JIRA NVGPU-1036
Change-Id: Id6dea92df371e71b22b54cd7a521fc22812f9b69
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929899
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-Call secured_sec2_start() to start SEC2 RTOS ucode execution
on SEC2 falcon in nvgpu_init_sec2_support() function
-Modified nvgpu_init_pmu_support() to do PMU bootstrap
from SEC2 RTOS by sending command.
-Added function nvgpu_sec2_bootstrap_ls_falcons() to
bootstrap LS falcon by taking falcon id as a parameter &
sending request to SEC2 RTOS with command
NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON.
-Modified method gr_gm20b_load_ctxsw_ucode() to
bootstrap FECS & GPCCS falcons using SEC2 RTOS
in cold boot & recovery path.
-Updated ldr_cfg parameters for SEC2 falcon
-Skip adding PMU ucode details to non-wpr blob preparation
to skip supporting of LS PMU falcon bootstrap.
JIRA NVGPUT-85
Change-Id: I5f6828e2737e247767814014801671327bb34a4e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832363
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-Created sec2_ipc.c to support SEC2 IPC.
-Defined nvgpu_sec2_cmd_post() to send command
to SEC2 RTOS from nvgpu along with dependent
methods like seq acquire/release, validate &
write cmd.
-Defined nvgpu_sec2_process_message() to
process message from SEC2 RTOS & route
to correct handler based on flag.
-Method sec2_process_init_msg() helps fetch
parameters sent from SEC2 RTOS to setup
queue, debug buffer as parameters.
-Created sec2 ops under gops to access
sec2 engine specific HALs.
-Defined nvgpu_sec2_queue_init() init
command & message for SEC2 RTOS using
common falcon queue.
-Made Makefile changes to include sec2_ipc.c for build
JIRA NVGPUT-82
Change-Id: I6e4c2d6ec71aa61a543f34680d1412167c9a8cc6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1828034
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-Created struct nvgpu_sec2 to hold members
related to SEC2-RTOS ucode support in header file
sec2.h
-Created nvgpu_sec2 variable under struct gk20a.
-Created NVGPU_SUPPORT_SEC2_RTOS enable flag
to enable SEC2 RTOS support.
-Defined method nvgpu_init_sec2_support() to
init SEC2 RTOS support by performing s/w setup like
mutex-init, sequence-init & add support
for remove_support.
-Defined method nvgpu_sec2_destroy() to deinit
SEC2 RTOS support.
-Added nvgpu_init_sec2_support()/nvgpu_sec2_destroy()
as part gk20a_finalize_poweron()/gk20a_prepare_poweroff()
sequence based on NVGPU_SUPPORT_SEC2_RTOS enable flag
-Assigned g->sec2->flcn to point to g->sec2_flcn to access
falcon.
-Made Makefile changes to include sec2.c to build
JIRA NVGPUT-80
Change-Id: Icdc8c25994e305427ad465a5a20e9ce533759a9e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1791955
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
