gpu: nvgpu: prepare common engine_queue.h

Some of the engine queue related defines are shared by PMU, SEC2 and
queue implementations and currently in gpmuif_cmn.h. Let us add
engine_queue.h header file to club all those defines together.

JIRA NVGPU-1994

Change-Id: I57a889e6d14d954d2660e513994bb87cbb1e5824
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019414
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/engine_queues/engine_fb_queue.c

@@ -23,12 +23,12 @@
 #include <nvgpu/log.h>
 #include <nvgpu/errno.h>
 #include <nvgpu/types.h>
-#include <nvgpu/pmuif/gpmuif_cmn.h>
 #include <nvgpu/flcnif_cmn.h>
 #include <nvgpu/nvgpu_mem.h>
 #include <nvgpu/pmu.h>
 #include <nvgpu/string.h>
 #include <nvgpu/kmem.h>
+#include <nvgpu/engine_queue.h>
 #include <nvgpu/engine_fb_queue.h>
 
 #include "engine_fb_queue_priv.h"

drivers/gpu/nvgpu/common/engine_queues/engine_mem_queue.c

@@ -22,6 +22,7 @@
 
 #include <nvgpu/lock.h>
 #include <nvgpu/pmu.h>
+#include <nvgpu/engine_queue.h>
 
 #include "engine_mem_queue_priv.h"
 #include "engine_dmem_queue.h"

drivers/gpu/nvgpu/common/pmu/pmu.c

@@ -26,6 +26,7 @@
 #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
 #include <nvgpu/pmuif/gpmu_super_surf_if.h>
 #include <nvgpu/enabled.h>
+#include <nvgpu/engine_queue.h>
 #include <nvgpu/barrier.h>
 #include <nvgpu/timers.h>
 #include <nvgpu/bug.h>

drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c

@@ -30,7 +30,6 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/firmware.h>
 #include <nvgpu/falcon.h>
-#include <nvgpu/engine_mem_queue.h>
 #include <nvgpu/mm.h>
 #include <nvgpu/io.h>
 #include <nvgpu/clk_arb.h>

drivers/gpu/nvgpu/common/pmu/pmu_ipc.c

@@ -28,7 +28,7 @@
 #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
 #include <nvgpu/pmuif/gpmu_super_surf_if.h>
 #include <nvgpu/falcon.h>
-#include <nvgpu/engine_mem_queue.h>
+#include <nvgpu/engine_queue.h>
 #include <nvgpu/engine_fb_queue.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/string.h>

drivers/gpu/nvgpu/common/sec2/sec2.c

@@ -26,6 +26,7 @@
 #include <nvgpu/sec2.h>
 #include <nvgpu/sec2if/sec2_if_sec2.h>
 #include <nvgpu/sec2if/sec2_if_cmn.h>
+#include <nvgpu/engine_queue.h>
 
 /* sec2 falcon queue init */
 int nvgpu_sec2_queue_init(struct nvgpu_sec2 *sec2, u32 id,

drivers/gpu/nvgpu/common/sec2/sec2_ipc.c

@@ -28,6 +28,7 @@
 #include <nvgpu/sec2.h>
 #include <nvgpu/sec2if/sec2_if_sec2.h>
 #include <nvgpu/sec2if/sec2_if_cmn.h>
+#include <nvgpu/engine_queue.h>
 
 static int sec2_seq_acquire(struct nvgpu_sec2 *sec2,
 	struct sec2_sequence **pseq)

drivers/gpu/nvgpu/include/nvgpu/engine_mem_queue.h

@@ -25,11 +25,6 @@
 
 #include <nvgpu/types.h>
 
-/* Queue Type */
-#define QUEUE_TYPE_DMEM 0x0U
-#define QUEUE_TYPE_EMEM 0x1U
-#define QUEUE_TYPE_FB   0x2U
-
 struct nvgpu_falcon;
 struct nvgpu_engine_mem_queue;
 

drivers/gpu/nvgpu/include/nvgpu/engine_queue.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_ENGINE_QUEUE_H
+#define NVGPU_ENGINE_QUEUE_H
+
+/* Queue Type */
+#define QUEUE_TYPE_DMEM 0x0U
+#define QUEUE_TYPE_EMEM 0x1U
+#define QUEUE_TYPE_FB   0x2U
+
+#define OFLAG_READ	0U
+#define OFLAG_WRITE	1U
+
+#define QUEUE_SET	(true)
+#define QUEUE_GET	(false)
+
+#define QUEUE_ALIGNMENT		(4U)
+
+#endif /* NVGPU_ENGINE_QUEUE_H */

drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -44,14 +44,6 @@
 #define  PMU_IS_MESSAGE_QUEUE(id)	\
 		((id) == PMU_MESSAGE_QUEUE)
 
-#define OFLAG_READ 	0U
-#define OFLAG_WRITE	1U
-
-#define QUEUE_SET		(true)
-#define QUEUE_GET		(false)
-
-#define QUEUE_ALIGNMENT		(4U)
-
 /* An enumeration containing all valid logical mutex identifiers */
 enum {
 	PMU_MUTEX_ID_RSVD1 = 0,