struct gr_gk20a defines boolean flag golden_image_initialized to
indicate if golden_image is initialized or not
common.gr.obj_ctx also added a flag of its own to check if golden_image
is ready
Add new API nvgpu_gr_obj_ctx_is_golden_image_ready() in
common.gr.obj_ctx unit to get status of golden_image
Use this new API everywhere to check if golden image is ready
Remove g->gr.ctx_vars.golden_image_initialized
Also remove ctx_mutex from struct gr_gk20a
Add new flag golden_image_initialized to struct nvgpu_pmu_pg and set it
when golden image is initialized. This is needed to avoid circular
dependency between GR and PMU
Jira NVGPU-3112
Change-Id: Id391294cede6424e15a9a9de29c40d013b509534
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099400
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Move gr_gk20a_handle_fecs_error from gr_gk20a.c to
nvgpu_gr_intr_handle_fecs_error in common.gr.intr unit
Move gr_gp10b_handle_fecs_error and gr_gv11b_handle_fecs_error
to hal.gr.intr unit
JIRA NVGPU-3016
Change-Id: I5b7c48ebfd7b13f497980c4d0b64d718649154bd
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103741
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Move gr_gp10b_handle_sm_exception from gr_gp10b to
gp10b_gr_intr_handle_sm_exception in hal.gr.intr unit
Move gr_gk20a_handle_sm_exception from gr_gk20a to
nvgpu_gr_intr_handle_sm_exception in common.gr.intr
Move nvgpu_report_gr_sm_exception to common.gr.intr
JIRA NVGPU-3016
Change-Id: I545ddca052122f87685f35f515831841a246dab3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103736
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Make a hal/mm/gmmu sub-unit for the GMMU HAL code. Also move the
gk20a specific HAL code there. gp10b will happen in the next patch.
This change also updates all the GMMU related HAL usage, of which
there is quite a bit. Generally the only change is a .gmmu needs to
be inserted into the HAL path. Each HAL init was also updated.
JIRA NVGPU-2042
Change-Id: I6c46bdfddb8e021f56103d9457fb3e2a226f8947
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099693
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g->ops.gr.get_preemption_mode_flags() hal is used to fetch information
on supported preemption modes and default preemption mode
Temporary struct nvgpu_preemption_modes_rec is used for this purpose
and is defined in gk20a/gr_gk20a.h right now.
Split above hal into two separate hals and move them to hal.gr.init unit
g->ops.gr.init.get_supported__preemption_modes()
g->ops.gr.init.get_default_preemption_modes()
These hals now return respective flags in pointers passed in function
parameter list, so there is no need to use temporary structure anymore
Hence delete struct nvgpu_preemption_modes_rec
Implement gm20b/gp10b chip specific hals in hal.gr.init unit.
Delete g->ops.gr.get_preemption_mode_flags() hal
Jira NVGPU-3126
Change-Id: I84f507fcd8d122bb7f0ecf697e8b4f16c9339ce1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102455
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Basic units like fifo, rc are having dependency on
gr_falcon. Avoided outside gr units dependency on gr_falcon
by moving following functions to gr:
int nvgpu_gr_falcon_disable_ctxsw(struct gk20a *g,
struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_disable_ctxsw(struct gk20a *g);
int nvgpu_gr_falcon_enable_ctxsw(struct gk20a *g,
struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_enable_ctxsw(struct gk20a *g);
int nvgpu_gr_falcon_halt_pipe(struct gk20a *g); ->
int nvgpu_gr_halt_pipe(struct gk20a *g);
HALs also moved accordingly and updated code to reflect this.
Also moved following data back to gr from gr_falcon:
struct nvgpu_mutex ctxsw_disable_mutex;
int ctxsw_disable_count;
JIRA NVGPU-3168
Change-Id: I2bdd4a646b6f87df4c835638fc83c061acf4051e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100009
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Move chip specific preempt code to hal/fifo
Move non-chip specific preempt code to common/fifo
Remove fifo.get_preempt_timeout
Rename gk20a_fifo_get_preempt_timeout -> nvgpu_preempt_get_timeout
Rename gk20a_fifo_preempt -> nvgpu_preempt_channel
Add fifo.preempt_trigger hal for issuing preempt
Add fifo.preempt_runlists_for_rc hal for preempting runlists during rc
Add fifo.preempt_poll_pbdma hal
Add nvgpu_preempt_poll_tsg_on_pbdma to be called from rc
JIRA NVGPU-3144
Change-Id: Idb089acaa0c6ca08de17487c3496459a61f0bcd4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100819
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Add esr_bpt_pending_events hal to report the type of
esr_bpt_pending_events to isr to process.
Add hal functions in gr instead of moving to gr.intr unit, as it
is part of non safety code.
JIRA NVGPU-1891
Change-Id: I70d75686042f97aa0e820d7982e95354971c9074
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100669
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MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. This patch contains fixes for all 17.7 violations
in the following units:
- nvgpu.common.hal.fifo.runlist
- nvgpu.common.hal.fifo.fifo
JIRA NVGPU-3039
Change-Id: I9483f5cb623cfe36d6b26e41c33f124c24710c08
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098765
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gfxp_wfi_timeout_count/unit fields were stored in gr_gk20a.ctx_vars
struct so that any user could configure them through sysfs nodes
But the sysfs nodes are legacy and not being actively used by anyone.
Hence delete the sysfs nodes to configure these fields.
Since the gfxp timeout unit/count can now be statically programmed,
make following changes
- remove g->ops.gr.init_gfxp_wfi_timeout_count() hal
- remove g->ops.gr.get_max_gfxp_wfi_timeout_count() hal
- update g->ops.gr.init.preemption_state() hals to configure the values
using macros instead of caller passing the values
- update g->ops.gr.init.gfxp_wfi_timeout() hals to configure the values
using macros instead of caller passing the values
Finally, we don't need to store gfxp_wfi_timeout_count/unit fields
anymore, hence delete them from gr_gk20a.ctx_vars
Jira NVGPU-3112
Change-Id: Idbe5ab3053228dd177aca253545aac36d38ca8ad
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100219
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Debug boolean flag dump_ctxsw_stats_on_channel_close is right now stored
in gr_gk20a.ctx_vars struct
This flag logically is property of gr.ctx units since it indicates
whether each context should dump ctxsw stats on channel/context close
Move this flag to struct nvgpu_gr_ctx_desc and remove it from
gr_gk20a.ctx_vars
Expose below API from gr.ctx unit to check if flag is set
nvgpu_gr_ctx_desc_dump_ctxsw_stats_on_channel_close()
Move debugfs creation code to create corresponding debugfs to
gr_gk20a_debugfs_init() and change debugfs type from "u32" to "file"
Struct gr.gr_ctx_desc is created only during first poweron.
Return error if this struct is not available.
Remove unnecessary initialization of this variable from platform
specific probe functions
Jira NVGPU-3112
Change-Id: Id675e047237f82e9b8198a42082e99c95824578f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099399
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Debug boolean flags force_preemption_gfxp and force_preemption_cilp are
right now stored in gr_gk20a.ctx_vars struct
These flags logically are property of gr.ctx units since they indicate
whether each context should be forced to gfxp/cilp preemption mode by
default
Move these flags to struct nvgpu_gr_ctx_desc and remove them from
gr_gk20a.ctx_vars
Expose below APIs from gr.ctx unit to check if flags are set
nvgpu_gr_ctx_desc_force_preemption_gfxp()
nvgpu_gr_ctx_desc_force_preemption_cilp()
Move debugfs creation code to create corresponding debugfs to
gr_gk20a_debugfs_init() and change debugfs type from "u32" to "file"
Struct gr.gr_ctx_desc is created only during first poweron.
Return error if this struct is not available.
Remove unnecessary initialization of these variables from platform
specific probe functions
Jira NVGPU-3112
Change-Id: I8b2de27f0c71dd2ea5abcf94221c2e15c80073ea
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099398
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Removed unused struct from gr_gk20a.h
Change static allocation for struct gr_gk20a to dynamic type.
Change all the files that being affected by that change.
Call gr allocation from corresponding init_support functions, which
are part of the probe functions.
nvgpu_pci_init_support in pci.c
vgpu_init_support in vgpu_linux.c
gk20a_init_support in module.c
Call gr free before the gk20a free call in nvgpu_free_gk20a.
Rename struct gr_gk20a to struct nvgpu_gr
JIRA NVGPU-3132
Change-Id: Ief5e664521f141c7378c4044ed0df5f03ba06fca
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095798
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Renamed and moved from fifo_gk20a.c to common/fifo/engines.c
gk20a_fifo_should_defer_engine_reset -> nvgpu_engine_should_defer_reset
Renamed and moved from fifo_gk20a.c to common/fifo/channel.c
gk20a_fifo_deferred_reset -> nvgpu_channel_deferred_reset_engines
JIRA NVGPU-1314
Change-Id: Ifc32ff4dde398143b83c2c1b6fab896142574240
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093910
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Rename the two native GPU GMMU map/unmap functions and update the
HAL initializations to reflect this:
gk20a_locked_gmmu_map -> nvgpu_gmmu_map_locked
gk20a_locked_gmmu_unmap -> nvgpu_gmmu_unmap_locked
This matches what other units do for handling vGPU "HAL" indirection.
Also move the function declarations to <nvgpu/gmmu.h> since these are
shared among all non-vGPU chips. But since these are still technically
HAL operations they should never be called directly. This is a bit of
an organixational issue that I have not thought through hwo to solve
yet.
Ideally they would go into a "hal/mm/gmmu/" include somewhere, but
that A) doesn't yet exist, and B) those are chip specific; these
functions are native specific. Ugh.
JIRA NVGPU-2042
Change-Id: Ibc614f2928630d12eafcec6ce73019628b44ad94
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099692
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Move the nvgpu_report_gr_exception call from gr_gk20a to
gr_intr.c as nvgpu_gr_intr_report_exception
Move local function gk20a_gr_get_channel_from_ctx to gr_intr.c
as nvgpu_gr_intr_get_channel_from_ctx
JIRA NVGPU-1891
Change-Id: I21521ad50989582d8f166a98a21ea3b1dcd3bbff
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098229
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Add a new MM HAL directory to contain all MM related HAL units.
As part of this change add cache unit to the MM HAL. This contains
several related fixes:
1. Move the cache code in gk20a/mm_gk20a.c and gv11b/mm_gv11b.c to
the new cache HAL. Update makefiles and header includes to take
this into account. Also rename gk20a_{read,write}l() to their
nvgpu_ variants.
2. Update the MM gops: move the cache related functions to the new
cache HAL and update all calls to this HAL to reflect the new
name.
3. Update some direct calls to gk20a MM cache ops to pass through
the HAL instead.
4. Update the unit tests for various MM related things to use the
new MM HAL locations.
This change accomplishes two architecture design goals. Firstly it
removes a multiple HW include from mm_gk20a.c (the flush HW header).
Secondly it moves code from the gk20a/ and gv11b/ directories into
more proper locations under hal/.
JIRA NVGPU-2042
Change-Id: I91e4bdca4341be4dbb46fabd72622b917769f4a6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095749
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Move zcull size initialization to hal.gr.zcull unit.
This removes zcull dependency on falcon unit
Add new variable zcull_image_size to gr_gk20a.ctx_vars struct
Pass the size to nvgpu_gr_zcull_init()/vgpu_gr_init_gr_zcull() as
parameter to initialize zcull info
Jira NVGPU-3112
Change-Id: I54d966073dad658b4aad3a529f44c0478208b10c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098507
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Use API nvgpu_gr_obj_ctx_get/set_golden_image_size() exposed by
gr.obj_ctx unit to get/set size of golden image
Call nvgpu_gr_obj_ctx_init() from vgpu_gr_init_gr_setup_sw() to
initialize golden image size in gr.obj_ctx unit even on vGPU
Move g->ops.gr.falcon.init_ctx_state() call early in
vgpu_gr_init_gr_setup_sw() so that gr.ctx_vars struct is prepared
before fields in it accessed during rest of GR initialization
Jira NVGPU-3112
Change-Id: Ie827ad6f30cc3d931519a1f9a709861d26f8da26
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096162
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Add new API nvgpu_gr_hwpm_map_get_size() in gr.hwpm_map unit to get
size of hwpm_map.
Use this API to get size and allocate each pm_ctx
Move nvgpu_gr_hwpm_map_init() call to gr.gr unit in gr_init_setup_sw()
instead of calling it from gr.falcon unit
Add nvgpu_gr_hwpm_map_init() to vGPU initialization to initialize
hwpm_map size on vGPU
Jira NVGPU-3112
Change-Id: Ifc669dcc9ecae273cea6978f5639f312cd451019
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096160
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Added new function to add require sw initionaltions. before enabling
gr hw. Added nvgpu_netlist_init_ctx_vars and nvgpu_gr_falcon_init_support
as part of this function:
int nvgpu_gr_prepare_sw(struct gk20a *g)
Moved following structure defs from gr_gk20a.h to gr_falcon.h and
renamed appropriately:
gk20a_ctxsw_ucode_segment -> nvgpu_ctxsw_ucode_segment
gk20a_ctxsw_ucode_segments -> nvgpu_ctxsw_ucode_segments
Moved following struct to gr_falcon_priv.h:
gk20a_ctxsw_ucode_info -> nvgpu_ctxsw_ucode_info
Moved following data from struct gk20a to new structure in gr_falcon_priv.h
struct nvgpu_gr_falcon:
struct nvgpu_mutex ctxsw_disable_lock;
int ctxsw_disable_count;
struct gk20a_ctxsw_ucode_info ctxsw_ucode_info;
Also moved following data from gr_gk20.h to struct nvgpu_gr_falcon:
struct nvgpu_mutex fecs_mutex;
bool skip_ucode_init;
wait_ucode_status
GR_IS_UCODE related enums
eUcodeHandshakeInit enums
Now add a pointer to this new data structure from struct gr_gk20a to
access gr_falcon related data and modified code to reflect this
change:
struct nvgpu_gr_falcon *falcon;
Added following functions to access gr_falcon data:
struct nvgpu_mutex *nvgpu_gr_falcon_get_fecs_mutex(
struct nvgpu_gr_falcon *falcon);
struct nvgpu_ctxsw_ucode_segments *nvgpu_gr_falcon_get_fecs_ucode_segments(
struct nvgpu_gr_falcon *falcon);
struct nvgpu_ctxsw_ucode_segments *nvgpu_gr_falcon_get_gpccs_ucode_segments(
struct nvgpu_gr_falcon *falcon);
void *nvgpu_gr_falcon_get_surface_desc_cpu_va(
struct nvgpu_gr_falcon *falcon);
JIRA NVGPU-1881
Change-Id: I9100891989b0d6b57c49f2bf00ad839a72bc7c7e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2091358
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Add new hal g->ops.gr.init.get_patch_slots() in hal.gr.init unit to get
patch slot count. Remove g->ops.gr.get_patch_slots().
Move corresponding functions to hal.gr.init unit
This hal does not need to be set for vGPU since it is not called in
that case
Jira NVGPU-2961
Change-Id: Ide488ae93af53a755da95faa268563070bd24bea
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2097533
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Add three hals in gr.falcon
- fecs_host_intr_status
This reads the fecs_host_intr_status, set the variables in the
nvgpu_fecs_host_intr_status struct to report back for gr to handle the
interrupts properly
- fecs_host_clear_intr
This helps to clear the needed bits in fecs_host_intr.
- read_fecs_ctxsw_mailbox
This reads the ctxsw_mailbox register based on register index.
Use these hals in gk20a_gr_handle_fecs_error and
gp10b_gr_handle_fecs_error functions.
JIRA NVGPU-1881
Change-Id: Ia02a254acc38e7e25c7c3605e9f1dda4da898543
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093917
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Modify read_pending_interrupts hal to report the pending gr interrupt
bit back to isr to process.
semaphore_timeout interrupt bit is removed after gk20a chip.
Remove that bit checking from the isr function.
Remove some static functions for handling interrupt, which only calls
gk20a_gr_set_error_notifier. Call that function directly from isr
JIRA NVGPU-3016
Change-Id: Ic7084f038114fbce6d6b5c10a806dee6280e5c0a
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2092876
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Create common/fifo/pbdma.c and move pbdma common code:
- nvgpu_pbdma_setup_sw
- nvgpu_pbdma_cleanup_sw
- nvgpu_pbdma_find_for_runlist
- nvgpu_pbdma_init_intr_descs
Moved the following HAL from fifo to pbdma
- fifo.find_pbdma_for_runlist -> pbdma.find_for_runlist
Added the following HALs
- fifo.init_pbdma_map
- pbdma.setup_sw
- pbdma.cleanup_sw
Jira NVGPU-2950
Change-Id: I17802ee61de669c3e17792b4505efb5e2bf530d3
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2092999
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