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233 Commits

Author SHA1 Message Date
Vedashree Vidwans
8f4b8e2b4e gpu: nvgpu: fix misra violations nvgpu.common.nvgpu 
MISRA Rule 10.4 requires both right and left operand to have same
essential type.
MISRA Rule 13.5 doesn't allow right hand operand of logical operator to
not have persistent side effects.

This patch fixes rule 10.4 and 13.5 in nvgpu/include/nvgpu/safe_ops.h.

Jira NVGPU-3737

Change-Id: If11c800df1bd74d68a8e2c99000de43fe1b7edc8
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2143924
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-07-02 03:04:52 -07:00
Nitin Kumbhar
c69c5a7a60 gpu: nvgpu: use safe ops in ALIGN and ALIGN_MASK 
Shortcomings of ALIGN macros:
- ALIGN_MASK down aligns when there is an wrapping/overflow instead of
  throwing an error. This can affect the size assumptions.
- Alignment a's check will be bypassed when ALIGN_MASK is directly
  used.

Fix these issues by 1) adding compile time error for non-unsigned type
arguments 2) using unsigned type safe ops for addition and subtraction.

Also, change users of ALIGN to pass unsigned types only.

JIRA NVGPU-3515
Jira NVGPU-3411

Change-Id: I5b94a262e09aad473c420af750ead6b0f9d36a9b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128382
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-28 08:56:27 -07:00
Vinod G
7ee75980cc gpu: nvgpu: add graphics flag for gfxp 
Initialize the compute preemption mode to CTA as default,
if the graphics flag is defined. Otherwise it is set to WFI as default.

Jira NVGPU-3580

Change-Id: I55ecc3715388951dd8d2fa9f6a15133e0bf3b939
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2143999
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-28 01:57:23 -07:00
Vinod G
72f0c22377 gpu: nvgpu: Fix MISRA 10.3 error in common.gr unit 
Fix MISRA C-2012 Rule 10.3 error in common.gr unit
misra_c_2012_rule_10_3_violation: Implicit conversion of
"!!(gr->ctxsw_disable_count < 0)" from essential type "boolean" to
different or narrower essential type "signed 32-bit int".

Jira NVGPU-3622

Change-Id: I27fb1aa64906242230678dff345307eb0a2d7bdc
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2140940
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-26 15:05:12 -07:00
Seshendra Gadagottu
e364102f9a gpu: nvgpu: add graphics flag for gfxp related code 
Move GFXP related code under CONFIG_NVGPU_GRAPHICS flag.
Keep the NVGPU_PREEMPTION_MODE_GRAPHICS_WFI support.

JIRA NVGPU-3415

Change-Id: Ie690ac66df4b94eb113a5898d94a892fe0ce7b11
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2135427
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-24 02:46:03 -07:00
Seshendra Gadagottu
7ed189de44 gpu: nvgpu: fix CERT INT30-C in common.gr.falcon 
Fixed CERT C error by using nvgpu_gr_checksum_u32:
segments->boot_signature += bootimage[i]; -->
	segments->boot_signature = nvgpu_gr_checksum_u32(
				segments->boot_signature, bootimage[i]);

JIRA NVGPU-3622

Change-Id: I01de116ba2a8afacb8a93be7b88e356a48122c5a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132547
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-21 01:06:16 -07:00
Sagar Kamble
5d37a9e489 gpu: nvgpu: compile out sim changes from safety build 
As sim is non-safe unit compile it out. Also removed FMODEL related
nvgpu changes and unit tests from the safety build.

JIRA NVGPU-3527

Change-Id: I22c83e195a09f9150fb6f5a3afff91df2ea075b9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2139455
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-20 16:05:33 -07:00
Rajesh Devaraj
ab70c2e80f gpu: nvgpu: report class/method related errors 
This patch adds support to report class/method related errors to 3LSS.
Specifically, it adds the following service ID:
NVGUARD_SERVICE_IGPU_PGRAPH_SWERR_ILLEGAL_ERROR

JIRA NVGPU-3458
JIRA NVGPU-3461

Change-Id: I9b28ed3074f664254347e059ac699470f95610b3
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2136301
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-18 01:37:43 -07:00
Deepak Nibade
1112af9f8c gpu: nvgpu: add flag for global fecs trace buffer index 
Add compile time flag check CONFIG_NVGPU_FECS_TRACE for
NVGPU_GR_GLOBAL_CTX_FECS_TRACE_BUFFER

Also add the flag check for setting NVGPU_FECS_TRACE_* characteristics
flag

Jira NVGPU-3506

Change-Id: I57f1538c852834b9be075a7b56b79fd699c04024
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132259
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:06:14 -07:00
Deepak Nibade
436549b9bf gpu: nvgpu: add cilp flag for CILP support 
Add CONFIG_NVGPU_CILP flag for CILP support across all the units

Jira NVGPU-3506

Change-Id: I0c71d38f9db6f00599a5070a8cb9d75d5b5fc351
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132258
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:05:59 -07:00
Deepak Nibade
4ac27a24bb gpu: nvgpu: add debugger flag for gr.utils unit 
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
common.gr.utils unit.

Jira NVGPU-3506

Change-Id: Iea551df287e06602949b3c2c33ebe565f0a0c921
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132257
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:05:44 -07:00
Deepak Nibade
6ac3fc30c7 gpu: nvgpu: add debugger flag for gr.ctx unit 
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
common.gr.ctx unit.

Jira NVGPU-3506

Change-Id: I42becd6404eb12b39dca7815849425128e7e42d8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132256
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:05:34 -07:00
Deepak Nibade
1792e6b820 gpu: nvgpu: add debugger flag for gr.global_ctx unit 
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
common.gr.global_ctx unit.

Jira NVGPU-3506

Change-Id: I9baf468c17b9c6a2a64275ac191242fa8e01b0e1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132255
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:05:24 -07:00
Deepak Nibade
1239bf67a5 gpu: nvgpu: add debugger flag for hal.gr.ctxsw_prog unit 
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
hal.gr.ctxsw_prog unit
Also add this flag for PM context allocation/free

Jira NVGPU-3506

Change-Id: Ib40569c7617b8b8aa3343fc89f3d8f30b1d21aa6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132254
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:05:14 -07:00
Seshendra Gadagottu
5943f5fc9d gpu: nvgpu: fix CERT EXP34-C in common.gr.falcon 
Fixed CERT EXP34-C error in gr_falcon driver by checking for valid
nvgpu_firmware pointer, before calling nvgpu_release_firmware.

JIRA NVGPU-3622

Change-Id: Ief4973ce4b73aa5348460632693d18e6104eda47
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134674
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 22:19:11 -07:00
Seshendra Gadagottu
b2ed105fe5 gpu: nvgpu: fix CERT-C errors in common.gr.falcon 
Used nvgpu_safe_mult_u32 function for u32 multiplications to avoid
CERT INT 30-C errors.

JIRA NVGPU-3622

Change-Id: Id945910a586c00be0f0cdad941b17023db66b23b
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134621
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 22:18:55 -07:00
Vinod G
6110bcf586 gpu: nvgpu: Fix MISRA 17.7 errors in gr.intr unit 
Fix MISRA 17.7 errors in gr.intr unit
misra_c_2012_rule_17_7_violation: The return value of a non-void
function is unused.

Jira NVGPU-3621

Change-Id: I7b03b8165a628decce66bf886625fe001db76a01
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134530
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 20:56:57 -07:00
Sagar Kamble
3f08cf8a48 gpu: nvgpu: rename feature Make and C flags 
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>

s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG

JIRA NVGPU-3624

Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130290
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 09:46:24 -07:00
Vinod G
1daaf83dce gpu: nvgpu: Fix CERT ARR37-C errors in common.gr.ctx unit 
Cert_arr37_c_violation: Using arithmetic operator on address which
points to non-array object.
Assign all pointer operands to array's 0th index address.

Jira NVGPU-3585

Change-Id: I59c213ed6d17d2bfb6f58c649a1ec151fba2c72b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133863
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 05:06:06 -07:00
Vinod G
0c13e9e8ad gpu: nvgpu: Fix CERT INT30-C errors in common.gr 
Fix CERT INT30-C erros in common.gr units

Unsigned integer operation may wrap. Use safe_ops macro
to fix the wrap errors.

Jira NVGPU-3585

Change-Id: I76127d8d58e1b5516370e78432754a7e7091e7be
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132588
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 07:48:58 -07:00
Deepak Nibade
c5f5eb896c gpu: nvgpu: add debugger flag for hwpm_map units 
Add NVGPU_DEBUGGER flag for common.gr.hwpm_map and
common.hal.gr.hwpm_map units

Jira NVGPU-3505

Change-Id: I5c9b6f98c7a8f536f5a8492febaa6140ef2adb6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130147
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 16:28:14 -07:00
Mahantesh Kumbar
b691df5a02 gpu: nvgpu: compile out PMU members & headers for safety 
-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files

JIRA NVGPU-3418

Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 06:55:58 -07:00
Vinod G
20b974e724 gpu: nvgpu: Add flag to rop_mapping hal function 
Add NVGPU_GRAPHICS flag to support the rop_mapping hal function and
files which refer this function.
Use only when this flag is defined.

Jira NVGPU-3584

Change-Id: I49b10bb772306ba20004b3836596ea43cf0e1775
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130649
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-05 22:56:21 -07:00
Vinod G
1ad54446da gpu: nvgpu: Add flag to map_tiles functions 
Add NVGPU_GRAPHICS flag to support the nvgpu_gr_config_init_map_tiles
and map_tiles related functions and variables.
Use only when this flag is defined.

Jira NVGPU-3583

Change-Id: Ib31a7445bcc573a127d1902bc19fc2aae9548d0f
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130616
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-05 22:56:12 -07:00
Thomas Fleury
97762279b7 gpu: nvgpu: make nvgpu_init_mutex return void 
Make the nvgpu_init_mutex function return void.
In linux case, this doesn't affect anything since mutex_init
returns void.
For posix, we assert() and die if pthread_mutex_init fails.

This alleviates the need to error inject for _every_
nvgpu_mutex_init function in the driver.

Jira NVGPU-3476

Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130538
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-05 10:25:52 -07:00
Divya Singhatwaria
8618135d6e gpu: nvgpu: Protect elpg_stat access 
- Protect the access of pmu->pg->elpg_stat using
  g->can_elpg protection
- Also, in pg public functions keep a check for 
  if lspmu and pg features are enabled.

JIRA NVGPU-3573

Change-Id: If4f25d4ab9df5e3e7257aaa9ed1e6d1fb9e431cf
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128351
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-04 14:15:08 -07:00
Seema Khowala
a72bfa63b2 gpu: nvgpu: Add NVGPU_FEATURE_POWER_PG compiler flag 
This flag is added to compile out below features from
safety build
-elpg

JIRA NVGPU-3425

Change-Id: I439edb444a4ebe1732a379aecbb0ffc8b48eb97c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127449
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-04 12:05:49 -07:00
Vinod G
9b163a0611 gpu: nvgpu: Fix CERT INT30-C errors in gr.intr unit 
Fix CERT INT30-C errors in gr.intr unit.
Use safe_ops functions nvgpu_safe_mult_u32 and
nvgpu_safe_cast_u32_to_s32 for multiplication and casting operations.

Jira NVGPU-3412

Change-Id: Ief3d1fe39ace9ba49eb839c823179ef82bacd85f
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129768
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-03 16:47:10 -07:00
Vinod G
46a078f384 gpu: nvgpu: Add flag checking for ZCULL code in gr.config 
Add NVGPU_GRAPHICS flag checking for ZCULL specific codes in gr.config.
This flag is disabled for safety build now.

Jira NVGPU-3550

Change-Id: Ib15ccdcb083731207d0684e3de4b2f24e05edbcd
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128611
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-03 16:46:26 -07:00
Seshendra Gadagottu
773c27dab5 gpu: nvgpu: fix CERT-C issue in common gr falcon 
Fix CERT INT30-c issue in gr falcon driver replacing
u32 arithmetic operation with nvgpu_safe_add_u32.

Also replaced SZ_256 with 256U to avoid mixed math calculation
with u32 and UL.

JIRA NVGPU-3413

Change-Id: If4f52845a78b7dc0c7936040d759471ba2e5ffc1
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126840
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-03 09:54:42 -07:00
Deepak Nibade
d16ddb244f gpu: nvgpu: remove g->ops.gr.halt_pipe hal 
Hal API g->ops.gr.halt_pipe() is defined in unsafe unit hal.gr.gr
It is called from safe unit, and it calls into API
g->ops.gr.falcon.ctrl_ctxsw() which is also safe

Hence get rid of unsafe API g->ops.gr.halt_pipe().
Caller now directly calls hal.gr.falcon API to halt pipe

Jira NVGPU-3506

Change-Id: I5439cb79431795fc7c22384832cf632d6db03316
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127755
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-03 04:15:41 -07:00
Deepak Nibade
e40994c884 gpu: nvgpu: add NVGPU_DEBUGGER flag for SM exception handling 
Trap handling and SM preprocessing is not needed in safety build i.e.
when NVGPU_DEBUGGER is false

Add NVGPU_DEBUGGER flag for all unsafe processing.

In safety build we only report the SM exceptions and return error
so that recovery is triggered

Also add flag for gr_intr_post_bpt_events() since event handling
is not needed in safety build

Jira NVGPU-3506

Change-Id: I660930fdb185b82c0adb612decbfd3d014ce2524
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127754
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-03 04:15:32 -07:00
Deepak Nibade
0908547ad2 gpu: nvgpu: move some interrupt hals to hal.gr.intr unit 
Move some interrupt handling hals from hal.gr.gr unit to hal.gr.intr
unit as below

g->ops.gr.intr.set_hww_esr_report_mask()
g->ops.gr.intr.handle_tpc_sm_ecc_exception()
g->ops.gr.intr.get_esr_sm_sel()
g->ops.gr.intr.clear_sm_hww()
g->ops.gr.intr.handle_ssync_hww()
g->ops.gr.intr.log_mme_exception()
g->ops.gr.intr.record_sm_error_state()
g->ops.gr.intr.get_sm_hww_global_esr()
g->ops.gr.intr.get_sm_hww_warp_esr()
g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask()
g->ops.gr.intr.get_sm_hww_warp_esr_pc()
g->ops.gr.intr.tpc_enabled_exceptions()
g->ops.gr.intr.get_ctxsw_checksum_mismatch_mailbox_val()

Rename gv11b_gr_sm_offset() to nvgpu_gr_sm_offset() and move to
common.gr.gr unit

All of above functions and hals will be needed in safety build

Jira NVGPU-3506

Change-Id: I278d528e4b6176b62ff44eb39ef18ef28d37c401
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127753
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-03 04:15:23 -07:00
Seema Khowala
1e7405a5dc gpu: nvgpu: Add NVGPU_FEATURE_CHANNEL_TSG_CONTROL compiler flag 
This flag is added to compile out below features from
safety build
-set_preemption_mode
-channel_enable
-channel_disable
-channel_preempt
-channel_force_reset
-tsg_enable
-tsg_disable
-tsg_preempt
-tsg_event_id_ctrl
-post_event_id

JIRA NVGPU-3516

Change-Id: I935841db766f192f62598240c0e245a2959555be
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126829
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-31 16:55:43 -07:00
Vinod G
61fb688f1a gpu: nvgpu: Add flag checking for ZCULL code 
Add NVGPU_GRAPHICS flag checking for ZCULL specific codes.
Define NVGPU_GRAPHICS flag for ZCULL support.
This flag is disabled for safety build now.

Jira NVGPU-3550

Change-Id: Ifd571a5e64e8fb2dfe02a87458a2986681900a6b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127515
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-31 04:08:11 -07:00
Mahantesh Kumbar
90aee0086f gpu: nvgpu: rename NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU 
renamed NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU to follow
nvgpu naming standard
Compile out LS PMU files when PMU RTOS support is
disabled for safety build by setting NVGPU_LS_PMU
build flag to 0

JIRA NVGPU-3418

Change-Id: Ib09924ac25657e932723c10be573f2f701cb7bea
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127794
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-30 19:27:14 -07:00
Mahantesh Kumbar
b6dfba15fa gpu: nvgpu: Compile out PMU PG/LSFM code for safety 
Compile out PMU PG & LSFM calls called from other unit when PMU RTOS
support is disabled for safety build by setting NVGPU_LS_PMU build
flag to 0

NVGPU JIRA-3418

Change-Id: I6a5089b37344697ffb0cc9ad301f4e7cf03f9f55
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117770
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-30 19:25:32 -07:00
Vinod G
4eb8663bd6 gpu: nvgpu: Add flag checking for ZBC support 
Add NVGPU_GRAPHICS flag checking for ZBC specific codes.
This flag will be disabled for safety build later.

Jira NVGPU-3494

Change-Id: I0f6dc3ac61189fe398bf031e9021b341ff2a7b13
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127447
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-30 13:36:15 -07:00
Rajesh Devaraj
fcb7635a92 gpu: nvgpu: gops initialization for SDL 
This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
  reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.

Jira NVGPU-3237

Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-30 02:18:05 -07:00
Seema Khowala
31cbde4412 gpu: nvgpu: Add NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING compiler flag 
This flag is added to compile out below features from
safety build
-get_timeslice
-set_timeslice
-set_priority
-set_interleave
-reschedule_runlist
-boosted_ctx

JIRA NVGPU-3513

Change-Id: I9addacf96693195f05d216a177d5d4f670eba888
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124438
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-30 00:17:13 -07:00
Vinod G
595da8ce67 gpu: nvgpu: Fix CERT-C errors in gr.config unit 
Fix CERT INT30-C errors in gr.config unit

cert_violation: Unsigned integer operation may wrap

Use safe_ops macro for multiplication to do wrap checks.

Jira NVGPU-3408

Change-Id: I553ca78263d687abf3d06b90588df9a83fd28815
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126101
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-28 16:57:27 -07:00
Vinod G
cf2d37640d gpu: nvgpu: Fix CERT-C errors in gr.config unit 
Fix CERT INT30-C errors in gr.config unit

cert_violation: Unsigned integer operation may wrap

Use safe_ops macros for addition, multiplication and subtraction
to do wrap checks.

Jira NVGPU-3408

Change-Id: I96d9317eadcc747f493c27daec9ecab1f2fe36a2
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125202
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-27 02:46:41 -07:00
Seema Khowala
4cf2d2166c gpu: nvgpu: Add NVGPU_VPR compiler flag 
This flag is added to compile out vpr support for
safety build.

JIRA NVGPU-3518

Change-Id: I6646a39ff6f1b7fd0948aacc3ede4a7a48bec734
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123900
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-23 17:45:40 -07:00
Sagar Kamble
17607e6bc9 gpu: nvgpu: remove sec2 from the safety build 
Since dGPU support is not required for initial safety release, disable
features from dGPU. Remove sec2 to start.

JIRA NVGPU-3062

Change-Id: I4448ab0fde603bc749dfdec5646308490971e18f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119585
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-23 10:07:22 -07:00
Mahantesh Kumbar
3d1169544f gpu: nvgpu: alloc space for PMU's struct nvgpu_pmu at runtime 
Allocating space for struct nvgpu_pmu at run time as part of
nvgpu_pmu_early_init() stage and made required changes to
dependent fiels as needed.

JIRA NVGPU-1972

Change-Id: I2d1c86d713e533c256ba95b730aa2e9543a66438
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110109
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-23 00:56:55 -07:00
Mahantesh Kumbar
0a64f6cb2d gpu: nvgpu: PMU pmu.c/h header include cleanup 
Some headers are not required to include in pmu.c/h as
lot of PMU code restructure happened, so removed headers
which not required anymore.

JIRA NVGPU-1972

Change-Id: Iead7f049d167cdaaaf7c75c2a5e19ae7b068fe6b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110108
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-23 00:56:45 -07:00
Seshendra Gadagottu
c7cc1d1e2d gpu: nvgpu: fix CERT INT30-C in common.gr.falcon 
Fixed CERT INT30-C violations in common gr falcon driver
by using nvgpu_safe_add_u64 and nvgpu_safe_add_u32
for u32 arithmetic operations.

JIRA NVGPU-3413

Change-Id: I574af10aa3352b8f855632c886adac3fce3141c3
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122510
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 16:26:07 -07:00
Vinod G
cd02e4d70f gpu: nvgpu: Fix CERT INT30-C errors in gr intr unit 
Fix CERT INT30-C error in gr interrupt units

cert_violation: Unsigned integer operation may wrap.

Use nvgpu_safe_ops macros for addition and subtraction.

Jira NVGPU-3412

Change-Id: Id2d936e77959005616faf069aff6701789342456
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122474
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 15:15:59 -07:00
Vinod G
1f85c3190b gpu: nvgpu: Fix CERT INT31-C errors in hal.gr.init 
Fix CERT INT31-C errors in hal.gr.init unit.
cert-violation: Casting "array_size" from "unsigned long" to "int"
without checking its value may result in lost or misinterpreted data.

Use nvgpu_safe_cast_u64_to_u32 macro to covert size_t to u32

Jira NVGPU-3411

Change-Id: Ib160e43af683d5ca6a1cc86c4b9ee3322ddc971d
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119847
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 15:15:41 -07:00
Deepak Nibade
dfdd05a3d6 gpu: nvgpu: disable fecs trace support for safety builds 
Compile all files with fecs trace support only if flag
NVGPU_FECS_TRACE_SUPPORT is set

remove CONFIG_GK20A_CTXSW_TRACE checks from within the files

add POSIX file for fecs trace support for compilation with
make command

Jira NVGPU-3414

Change-Id: I205e3494ce94138ab6c6fccf7fbcefc41f953c77
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120276
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 10:36:04 -07:00