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gpu: nvgpu: fix CERT-C issue in common gr falcon

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Fix CERT INT30-c issue in gr falcon driver replacing
u32 arithmetic operation with nvgpu_safe_add_u32.

Also replaced SZ_256 with 256U to avoid mixed math calculation
with u32 and UL.

JIRA NVGPU-3413

Change-Id: If4f52845a78b7dc0c7936040d759471ba2e5ffc1
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126840
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-05-28 16:03:21 -07:00
committed by mobile promotions
parent d16ddb244f
commit 773c27dab5
1 changed files with 4 additions and 1 deletions
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5
drivers/gpu/nvgpu/common/gr/gr_falcon.c
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@@ -237,9 +237,12 @@ static int nvgpu_gr_falcon_init_ctxsw_ucode_vaspace(struct gk20a *g,
static void nvgpu_gr_falcon_init_ctxsw_ucode_segment(
struct nvgpu_ctxsw_ucode_segment *p_seg, u32 *offset, u32 size)
{
u32 ucode_offset;
p_seg->offset = *offset;
p_seg->size = size;
*offset = ALIGN(*offset + size, SZ_256);
ucode_offset = nvgpu_safe_add_u32(*offset, size);
*offset = ALIGN(ucode_offset, 256U);
}
static void nvgpu_gr_falcon_init_ctxsw_ucode_segments(