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22 Commits

Author SHA1 Message Date
srajum
069fe05dca gpu: nvgpu: remove whitelisting for wrongly reported violations by tool 
- Earlier we whitelisted wrongly reported static analysis violations
  by tool, raised coverity tool bugs for these cases.

- These bugs are fixed with new version of tool, so no need fo whitelisting.

JIRA NVGPU-7119

Change-Id: Ib2341db0d46fa7fac4c0cc9a6c1bdc8704377ef1
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2604365
(cherry picked from commit dc2d8ddaa409aefe0e04e0bacb3a8a977f6dbd64)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2677523
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-03-10 16:01:06 -08:00
shashank singh
29019dff6e gpu: nvgpu: remove round_up usage in safety build 
- In function gv11b_tsg_init_eng_method_buffers() PAGE_ALIGN can be used
  instead of round_up macro.
- In function nvgpu_posix_find_next_bit() rounding up of start does not
  seem to serve any purpose.

JIRA NVGPU-7057

Change-Id: I4a3a21e95a0f3aa38f7007de1f6959f1d878e511
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2614326
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2672107
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-02-23 11:08:31 -08:00
Peter Daifuku
f0f126d7cc gpu: nvgpu: posix: fix GPL dependencies in bitmap 
Fix up GPL issues in posix version of bitops.

Bug 2919200

Change-Id: I57fdb035b811f47e119cca2278431d3701717d89
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340983
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Terje Bergstrom
32db53d4e1 gpu: nvgpu: posix: Pass atomic types to atomic ops 
Atomic functions require the type of manipulated atomic to be of
_Atomic type.

Change-Id: I8cf417a2b15ef34488b82560b65d5abfbe67fde8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318385
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
ajesh
1c1dca5d6f gpu: nvgpu: avoid hard coded constants 
Replace the hard coded numeric constants in posix unit.

Jira NVGPU-4954

Change-Id: I9f57e2d60b44c942924c47a7e38c237c732b13b0
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2289633
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Philip Elcan
4874324ee5 gpu: nvgpu: whitelist MISRA 14.3 bugs 
Whitelist MISRA Rule 14.3 violations that are due to a bug in the
Coverity scanner documented in nvbug 2615925.

JIRA NVGPU-4031

Change-Id: Ib8e03641578f27a774b05758cb292236f720c3ba
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2198904
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vinod G
a2689970dc gpu: nvgpu: fix cert arr37 error in gr unit 
Fix CERT ARR37-C violations in gr unit
cert_arr37_c_violation: Performing pointer arithmetic in expression.

Make the pointer operand point to an array using index 0.

Jira NVGPU-3854

Change-Id: I11f1d4a3e74f7711f1e3b479785b1dbcc20fee75
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2169668
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-08-07 14:06:51 -07:00
ajesh
b095d73022 gpu: nvgpu: modify the ffs and fls interface 
Modify the ffs/fls interface function names to nvgpu_ffs and
nvgpu_fls.  The return bit values are numbered from 1 to 64.
A return value of 0 indicates an input of 0 value.

Jira NVGPU-3601

Change-Id: I1c151eeac1f94fe3b5b85bd5daf0488f75c5efa0
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146119
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-07-11 05:43:55 -07:00
ajesh
15afca04ba gpu: nvgpu: fix CERT C violations in bitops unit 
INT30-C Requires that unsigned integer operations do not wrap.
INT31-C Requires that integer conversions do not result in lost or
misinterpreted data.
Fix the violations of above rules in bitops unit.

Jira NVGPU-3601

Change-Id: I77bc56d2dda80aa05a4665c0b5762f6ecf99ea3f
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2139306
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-07-03 21:45:18 -07:00
Nitin Kumbhar
c69c5a7a60 gpu: nvgpu: use safe ops in ALIGN and ALIGN_MASK 
Shortcomings of ALIGN macros:
- ALIGN_MASK down aligns when there is an wrapping/overflow instead of
  throwing an error. This can affect the size assumptions.
- Alignment a's check will be bypassed when ALIGN_MASK is directly
  used.

Fix these issues by 1) adding compile time error for non-unsigned type
arguments 2) using unsigned type safe ops for addition and subtraction.

Also, change users of ALIGN to pass unsigned types only.

JIRA NVGPU-3515
Jira NVGPU-3411

Change-Id: I5b94a262e09aad473c420af750ead6b0f9d36a9b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128382
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-28 08:56:27 -07:00
ajesh
a6cbfca58c gpu: nvgpu: fix MISRA violations in bitops unit 
Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset.  OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.

Jira NVGPU-3545

Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129513
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 22:26:41 -07:00
Vinod G
4201f58e1e gpu: nvgpu: Add utils header for posix 
Move all definitions and functions other than type defines from types.h
to new header utils.h for posix.
Update files that use functions and defintions from utils.h

DIV_ROUND_UP macro is updated to use safe_ops.h calls to handle
the CERT-C wrap issues.

Jira NVGPU-3411

Change-Id: I9da3e9f255f39949287c615519f062fd8816aa04
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130453
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-07 17:05:23 -07:00
Nitin Kumbhar
69331cdfb7 gpu: nvgpu: posix: fix EXP32 CERT C violation 
Do not ignore volatile attribute of addr while assigning it to p.

Error: CERT EXP32-C:
drivers/gpu/nvgpu/os/posix/bitmap.c:227:
cert_violation: Access volatile variable "addr" through
 a nonvolatile reference.

Jira NVGPU-3560

Change-Id: I202b143e1818641b12f6552810953ac447348271
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122720
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 16:27:13 -07:00
ajesh
8901faae57 gpu: nvgpu: fix MISRA violations in bitops unit 
MISRA rule 21.1 states that #define and #undef shall not be used on
a reserved identifier or reserved macro name.  Fix violations of
rule 21.1 in bitops unit.
MISRA rule 21.2 states that a reserved identifier or macro name
shall not be declared.  Fix violations of rule 21.2 in bitops unit.

Jira NVGPU-3545

Change-Id: Ie551d7ce5e19287107403f2c991bcc55bd11a4e8
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125842
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-29 14:51:37 -07:00
ajesh
ff4de9c9c1 gpu: nvgpu: fix issues with ffs and __fls 
The LSB is position 1 for ffs and LSB is position 0 for __fls.  Fix the
issue with the return values of ffs and __fls to follow the mentioned
bit positions.

Jira NVGPU-2149

Change-Id: I4deab420c62217f8ad90683397c38530f88467d2
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107276
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-04-30 00:49:09 -07:00
Philip Elcan
13ad8142ef gpu: nvgpu: unit: fix valgrind errors in posix bitmap 
Fix cases where valgrind reported conditional jump or move depends on
uninitialised value(s)

JIRA NVGPU-3098

Change-Id: I5699d1f8539ec29e6f1bac6452e216c72c4d9007
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094640
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-12 15:34:10 -07:00
Philip Elcan
67caad40e9 gpu: nvgpu: unit: update misc atomics to use gcc builtins 
There were a few outliers in the unit tests that were still using old
style atomics (__sync_*). This updates those to use the new standard
builtins in GCC.

JIRA NVGPU-2842

Change-Id: Ib79e0fb48e7812b57aa4634ad96c37436c2b3923
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034217
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-03-07 19:04:29 -08:00
Adeel Raza
800d96865d gpu: nvgpu: posix: MISRA rule 15.6 fixes 
MISRA rule 15.6 requires that all if/else/loop blocks should be enclosed
by brackets. This patch adds brackets to single line if/else/loop blocks
in the POSIX code.

JIRA NVGPU-775

Change-Id: Idafd5a5068c23b850ad1b0b083550a75b35588c1
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011739
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-02-05 19:23:58 -08:00
Amurthyreddy
9aa74d5f86 gpu: nvgpu: MISRA 10.4 boolean fixes 
MISRA rule 10.4 doesn't allow arithmetic conversions on operands of
different essential type category.

Fix violations where an arithmetic conversion is performed on boolean
and non-boolean types.

JIRA NVGPU-994

Change-Id: I2af9937678462b632bb6ec6178e10d02104fc3bc
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832337
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2018-10-30 15:33:58 -07:00
Adeel Raza
dc37ca4559 gpu: nvgpu: MISRA fixes for composite expressions 
MISRA rules 10.6, 10.7, and 10.8 prevent mixing of types in composite
expressions. Resolve these violations by casting variables/constants to
the appropriate types.

Jira NVGPU-850
Jira NVGPU-853
Jira NVGPU-851

Change-Id: If6db312187211bc428cf465929082118565dacf4
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1931156
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2018-10-25 11:13:38 -07:00
Philip Elcan
8c4b073537 gpu: nvgpu: posix: fix implementation of fls() 
The POSIX implementation of fls() wasn't compliant with the Linux which
returns fls(0)=0 fls(1)=1, etc.

Bug found as result of JIRA NVGPU-1042.

Change-Id: Id0279e36332ffe236ed792c013c32f2da841f557
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1828361
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-09-20 12:58:50 -07:00
Alex Waterman
b15624b39b gpu: nvgpu: posix: move the posix dir to os 
Since the posix code is supporting a particular OS this code
should belong under os/ not common/.

Change-Id: Idf5f75b8ab9d614c9dd43ea23dab8df3c346c0ef
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1800658
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-08-17 13:54:25 -07:00