7 Commits

Author	SHA1	Message	Date
Seema Khowala	c0cf011600	gpu: nvgpu: move gk20a_decode_pbdma_chan_eng_ctx_status ... Moved from fifo_gk20a.c to common/fifo/fifo.c gk20a_decode_pbdma_chan_eng_ctx_status Renamed gk20a_decode_pbdma_chan_eng_ctx_status -> nvgpu_fifo_decode_pbdma_ch_eng_status JIRA NVGPU-2950 Change-Id: I10ec766a28b1b7dabd334bacfb76a6aa14f49fe6 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2094651 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-16 10:46:02 -07:00
Thomas Fleury	9f233a6ab4	gpu: nvgpu: add setup_sw and cleanup_sw for pbdma ... Create common/fifo/pbdma.c and move pbdma common code: - nvgpu_pbdma_setup_sw - nvgpu_pbdma_cleanup_sw - nvgpu_pbdma_find_for_runlist - nvgpu_pbdma_init_intr_descs Moved the following HAL from fifo to pbdma - fifo.find_pbdma_for_runlist -> pbdma.find_for_runlist Added the following HALs - fifo.init_pbdma_map - pbdma.setup_sw - pbdma.cleanup_sw Jira NVGPU-2950 Change-Id: I17802ee61de669c3e17792b4505efb5e2bf530d3 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2092999 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-12 01:15:59 -07:00
Seema Khowala	c99f13e842	gpu: nvgpu: move nvgpu_report_host_error ... Move nvgpu_report_host_error from gk20a/fifo_gk20a.c to common/fifo/fifo.c JIRA NVGPU-2011 Change-Id: Ia42c901edafa7bc11a8da4152b92293a5d131d10 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2093119 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-10 16:15:59 -07:00
Thomas Fleury	696d212718	gpu: nvgpu: move userd to separate unit ... Add userd unit under common/fifo Moved userd setup/cleanup from fifo: - nvgpu_userd_setup_sw - nvgpu_userd_cleanup_sw Moved common userd code from hals: - nvgpu_userd_init_slabs - nvgpu_userd_free_slabs - nvgpu_userd_init_channel Replaced the following hals - fifo.userd_gp_get - fifo.userd_gp_put - fifo.userd_pb_get - fifo.setup_userd - fifo.userd_entry_size With - userd.gp_get - userd.gp_put - userd.pb_get - userd.init_mem - userd.entry_size Also added the following hals - userd.setup_sw: init slabs and reserve userd gpu_va - userd.cleanup_sw: de-init slabs and free gpu_va - userd.setup_hw: setup writeback timeout Jira NVGPU-2713 Change-Id: Ide854a38531a3ce00e61045449ddd010c956bdeb Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2035116 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-22 06:25:55 -07:00
Thomas Fleury	30591ce1a7	gpu: nvgpu: move runlist_submit_lock to runlist ... runlist_submit_lock is used by runlist unit. Move initialization to nvgpu_runlist_setup_sw. Jira NVGPU-1306 Change-Id: I8476a12b51cd0831de700c793559d46cd43b784e Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2076707 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-20 16:26:24 -07:00
Thomas Fleury	6729d67f59	gpu: nvgpu: vpgu: use fifo common init/deinit code ... Native and vgpu were using different paths for fifo init/deinit code. Use same nvgpu_fifo_init_support for init code: nvgpu_fifo_init_support g->ops.fifo.setup_sw vgpu_fifo_setup_sw (NEW) Use same nvgpu_fifo_remove_support for deinit code: nvgpu_fifo_remove_support (NEW) g->ops.fifo.cleanup_sw (NEW) vgpu_fifo_cleanup_sw (NEW) Also implemented gk20a_fifo_cleanup_sw for native case. Jira NVGPU-1306 Jira NVGPU-2855 Change-Id: Iefe303cc224f804a206422e2efffda9da1616d89 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2029649 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-18 16:56:04 -07:00
Thomas Fleury	ffed5095db	gpu: nvgpu: move fifo init/deinit code to common ... Add fifo sub-unit to common.fifo to handle init/deinit code and global support functions. Split init into: - nvgpu_channel_setup_sw - nvgpu_tsg_setup_sw - nvgpu_fifo_setup_sw - nvgpu_runlist_setup_sw - nvgpu_engine_setup_sw - nvgpu_userd_setup_sw - nvgpu_pbdma_setup_sw Split de-init into - nvgpu_channel_cleanup_sw - nvgpu_tsg_cleanup_sw - nvgpu_fifo_cleanup_sw - nvgpu_runlist_cleanup_sw - nvgpu_engine_cleanup_sw - nvgpu_userd_cleanup_sw - nvgpu_pbdma_cleanup_sw Added the following HALs - runlist.length_max - fifo.init_pbdma_info - fifo.userd_entry_size Last 2 HALs should be moved resp. to pbdma and userd sub-units, when available. Added vgpu implementation of above hals - vgpu_runlist_length_max - vgpu_userd_entry_size - vgpu_channel_count Use hals in vgpu_fifo_setup_sw. Jira NVGPU-1306 Change-Id: I954f56be724eee280d7b5f171b1790d33c810470 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2029620 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-14 20:35:22 -07:00