Lakshmanan M
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55f472a0b7
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gpu: nvgpu: Use logical GPC id mask
Replaced logical GPC id mask instead of physical GPC id mask
for GPCCS falcon index mask programming required for multi-GR boot.
JIRA NVGPU-5650
Change-Id: I0fad31ea962d2f0bd069aa20deeea16ea29c307a
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2434229
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2020-12-15 14:13:28 -06:00 |
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Lakshmanan M
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0e7b6e27e8
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gpu: nvgpu: Add multi GR sec2 boot support
This CL covers the following code changes,
1) Added API to get the physical gpc id masks.
2) Added multi GR instance sec2 boot support for MIG.
JIRA NVGPU-5650
Change-Id: I16c6bd34b5e8d86ad807fafac4b2441c097eb3e2
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2419092
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2020-12-15 14:13:28 -06:00 |
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mkumbar
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b9050c51c1
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gpu: nvgpu: bootstrap enabled GPC's from SEC2
get floorswept GPC mask and convert to ucode required
index mask to bootstrap enabled GPC's using LS SEC2
RTOS ucode
Bug 200657884
Change-Id: I0b111bcfb2d4b2c24f67b45e8e93954aeb03d711
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2416107
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2020-12-15 14:13:28 -06:00 |
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mkumbar
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13ca3c9a37
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gpu: nvgpu: boot enabled GPC’s using SEC2 RTOS ucode
Read mask of GPC’s to boot only enabled GPC’s and discard
floorswept GPC.
Read GPC’s mask info need to send to SEC2 RTOS to bootstrap
enabled GPC’s.
JIRA NVGPU-5466
Change-Id: Id4ed7d4072730da8e128cd43af92a1a6b1aac8ad
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2394004
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2020-12-15 14:13:28 -06:00 |
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mkumbar
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7aa8447ef2
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gpu: nvgpu: sec2 LS falcon bootstrap update
Add LS Falcon instance and index mask param update to bootstrap
selected instance using nv_sec2_acr_cmd_bootstrap_falcon interface.
JIRA NVGPU-5468
Change-Id: Ief55755e69c82697a52fb1c50381c50313aa72e7
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2365588
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2020-12-15 14:13:28 -06:00 |
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Sagar Kamble
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bcbc87dc2e
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gpu: nvgpu: move pmu interface headers to include/nvgpu/pmu
Interface header files for PMU features are now moved under PMU header
files directory include/nvgpu/pmu. And fix bulk of coding style issues.
Update header file names and guards.
JIRA NVGPU-1971
Change-Id: Idf53fc09d8928d1b0a1cd16eef886de010dae06b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093006
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2019-04-13 12:33:52 -07:00 |
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Sagar Kamble
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974ad342fa
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gpu: nvgpu: update sec2.h header
Update sec2.c to not dereference struct gk20a and update sec2.h to
remove unneeded header files. Move sec2.h to include/nvgpu/sec2.
JIRA NVGPU-2074
Change-Id: I1a8f4b1913323693fae422ce27c4ec0ac29de24a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085752
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2019-04-10 09:26:56 -07:00 |
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Sagar Kamble
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8b304b4351
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gpu: nvgpu: prepare sec2 cmd unit
sec2_ipc.c now has the SEC2 command management functionality. Let us
rename it to sec2_cmd.c. Also update the header includes.
JIRA NVGPU-2074
Change-Id: I884829c6c68344f869c19b09130078ba413dc221
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085751
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2019-04-10 09:26:45 -07:00 |
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Sagar Kamble
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6eae6df6da
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gpu: nvgpu: create sec2 lsfm unit
Bootstrapping LS falcons is done by SEC2 by sending commands to SEC2
RTOS. This requires interaction with SEC2 cmd and msg units. Hence
prepare separate unit.
JIRA NVGPU-2074
Change-Id: I5a27b4eef3fa3f11bcaac8bd9494fe771b921cf9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085750
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2019-04-10 09:26:30 -07:00 |
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