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12 Commits

Author SHA1 Message Date
Ramesh Mylavarapu
d2d59d6206 gpu: nvgpu: add gsp ops to support cmd/msg 
Added all dependent gsp dependent ops. This include
read/write from/into EMEM, get Queue head/tail, engine
dependent ops and aperture settings.

NVGPU-6784

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: Ic780bfdcd2de593bf2e8f292756e3d1700610ad2
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2590940
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-10-01 09:29:55 -07:00
ajeshkv
118f8c1280 gpu: nvgpu: add support for gsp stress test 
Add debugfs entries to support GSP stress test and other
functionalities to enable the test.

JIRA CORERM-3382

Change-Id: Iab20fcfe78807e76e91c64716502a2f036ed4d18
Signed-off-by: ajeshkv <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2589390
Reviewed-by: Amit Pabalkar <apabalkar@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-10 16:02:43 -07:00
Ramesh Mylavarapu
ffd0d3962f gpu: nvgpu: gsp: gsp isr and debug trace support 
- Created GSP NVRISCV interrupt handle and
  respective functions and register reads.
- Created Debug trace support for GSP firmware.

NVGPU-7084

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I2728150c4db00403aa6e3c043bc19c51677dd9cf
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2589430
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-07 05:37:51 -07:00
Ramesh Mylavarapu
d328bff79e gpu: nvgpu: gsp NVRISCV load and bootstrap 
Changes:
- This change will only init gsp software
  state, nvgpu_gsp_bootstrap need to be called.
- CONFIG_NVGPU_GSP_SCHEDULER flag is created to
  compile out the gsp scheduler code when needed.
- Created GSP engine reset which is needed when
  ACR completed execution and need to load gsp fw.

NVGPU-6783

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I2ce43e512b01df59443559eab621ed39868ad158
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554267
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-07-15 17:21:03 -07:00
Pekka Jylhä-Ollila
8a72068508 Revert "gpu: nvgpu: gsp NVRISCV load and bootstrap" 
This reverts commit aef4b80acb.

Change-Id: I47e02bf97e6a3aaa9acdd7f5eec41518b31ee5dc
Signed-off-by: Pekka Jylhä-Ollila <pjylhaollila@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554105
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
 2021-07-05 06:01:52 -07:00
Ramesh Mylavarapu
aef4b80acb gpu: nvgpu: gsp NVRISCV load and bootstrap 
Changes:
- This change will only init gsp software
  state, nvgpu_gsp_bootstrap need to be called.
- CONFIG_NVGPU_GSP_SCHEDULER flag is created to
  compile out the gsp scheduler code when needed.
- Created GSP engine reset which is needed when
  ACR completed execution and need to load gsp fw.

NVGPU-6783

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I26263ee5bae07de056f676ed0fddc1193b5af82d
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2530438
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-07-04 13:34:51 -07:00
Sagar Kadamati
3e43f92f21 gpu: nvgpu: add ga10b & ga100 sources 
Mass copy ga10b & ga100 sources from nvgpu-next repo.
TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1

Jira NVGPU-4771

Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-06-17 12:56:16 -07:00
Mahantesh Kumbar
82c5ff8712 gpu: nvgpu: Deleting GSP HAL's GV100 support 
-Deleting GV100 from GSP HAL as GV100 is not supported
 anymore.
-Renamed all GSP related code to tu104 to deprecate GV100
 GSP support

JIRA NVGPU-3243

Change-Id: I2ce321ee045797133456d04871a3d7bb8a223911
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168245
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-08-05 23:01:19 -07:00
Mahantesh Kumbar
3ef34ac31c gpu: nvgpu: PMU/SEC2/GSP engine reset skip 
-Add a FUSA check to skip reset for PMU/SEC2/GSP engine's falcon
-On dGPU FUSA SKU, reset of HS falcons SEC2, PMU and GSP will be
 handled by HS falcon ucode, so, skip reset for PMU/SEC2/GSP
 in NvGPU.

JIRA NVGPU-3728

Change-Id: I956272771994b96e4115e67869bce7bd03193196
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2163560
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-07-30 07:36:48 -07:00
Thomas Fleury
4ef4939797 gpu: nvgpu: add base_shift and alloc_size ramin HALs 
Added the following HALs
- ramin.base_shift
- ramin.alloc_base

Use above HALs in mm, instead of using hw definitions.

Defined nvgpu_inst_block_ptr to
- get inst_block address,
- shift if by base_shift
- assert upper 32 bits are 0
- return lower 32 bits

Added missing #include for <nvgpu/mm.h>

Jira NVGPU-3015

Change-Id: I558a6f4c9fbc6873a5b71f1557ea9ad8eae2778f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077840
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-07 15:54:10 -07:00
Mahantesh Kumbar
a67729dcfc gpu: nvgpu: Create separate VM space for SEC2/GSP engine 
Currently SEC2/GSP uses the PMU VM space for memory access which adds
dependency on PMU, So, created separate VM space for SEC2/GSP of
size 32MB as currently used for ucode handling by these units.

SEC2/GSP VM space allocation happens if NVGPU_SUPPORT_SEC2_VM/
NVGPU_SUPPORT_GSP_VM enable flags set.

JIRA NVGPU-2910

Change-Id: I4dfe50a1c0adb7e83379bf6c15343fe57ff44c38
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077596
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-03-25 11:56:23 -07:00
Mahantesh Kumbar
a299b8857f gpu: nvgpu: Move HAL gsp code to hal/gsp folder 
Moved GSP HAL code from gv100/gsp_gv100.* to hal/gsp/gsp_gv100.*

JIRA NVGPU-2039

Change-Id: Id85d5355dcb2b0831afd177568a9a2ba3faec664
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2073675
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-03-22 08:47:12 -07:00