2 Commits

Author	SHA1	Message	Date
Sagar Kamble	51120a4361	gpu: nvgpu: access falcon HAL functions through g->ops ... Earlier falcon HAL ops were embedded in the falcon structure. For clear separation of common and HAL these ops will have to be accessed through g->ops.falcon interfaces. With these changes nvgpu_falcon_* functions directly call falcon gpu ops functions for falcon. Falcon registers and HAL functions are exported from falcon_gk20a.h. HAL files per platform are now updated with base falcon functions. Falcon software state such as is_falcon_supported, is_interrupt_enabled and flcn_base are set from software init functions defined per chip. JIRA NVGPU-2038 Change-Id: Ib1729d2833cd2c6c7b2c8ed7cbc17d4d6daeba73 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2023077 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-15 02:25:04 -07:00
Sagar Kamble	e86949f5a2	gpu: nvgpu: update NVDEC falcon base addr init ... NVDEC falcon base address was being set without invoking hal api. Remove FALCON_NVDEC_BASE. This patch defines gpu_ops.fb.falcon_base_addr hal api to get this base address. Currently gp106 and tu104 have these implemented. gv100 uses the gp106 hal interface. Also, don't initialize the base for non-supported falcons. JIRA NVGPU-1587 Change-Id: I0be759b8462ede9b85690a70431480afdee9602c Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1969427 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2018-12-12 15:14:05 -08:00