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gpu: nvgpu: update NVDEC falcon base addr init

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NVDEC falcon base address was being set without invoking hal api. Remove
FALCON_NVDEC_BASE. This patch defines gpu_ops.fb.falcon_base_addr hal api
to get this base address. Currently gp106 and tu104 have these
implemented. gv100 uses the gp106 hal interface.
Also, don't initialize the base for non-supported falcons.

JIRA NVGPU-1587

Change-Id: I0be759b8462ede9b85690a70431480afdee9602c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969427
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2018-12-10 11:12:54 +05:30
committed by mobile promotions
parent 2c09ee5cf0
commit e86949f5a2
14 changed files with 145 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/Makefile
View File

@@ -78,7 +78,9 @@ nvgpu-y += common/bus/bus_gk20a.o \
common/netlist/netlist_gp10b.o \
common/netlist/netlist_gv100.o \
common/netlist/netlist_gv11b.o \
common/netlist/netlist_tu104.o
common/netlist/netlist_tu104.o \
common/nvdec/nvdec_gp106.o \
common/nvdec/nvdec_tu104.o
# Linux specific parts of nvgpu.
nvgpu-y += \

2
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -158,6 +158,8 @@ srcs := os/posix/nvgpu.c \
common/boardobj/boardobjgrpmask.c \
common/boardobj/boardobjgrp_e255.c \
common/boardobj/boardobjgrp_e32.c \
common/nvdec/nvdec_gp106.c \
common/nvdec/nvdec_tu104.c \
pstate/pstate.c \
volt/volt_dev.c \
volt/volt_pmu.c \

5
drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c
View File

@@ -742,11 +742,6 @@ int gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = false;
break;
case FALCON_ID_NVDEC:
flcn->flcn_base = FALCON_NVDEC_BASE;
flcn->is_falcon_supported = false;
flcn->is_interrupt_enabled = false;
break;
default:
flcn->is_falcon_supported = false;
break;

2
drivers/gpu/nvgpu/common/falcon/falcon_gp106.c
View File

@@ -81,7 +81,7 @@ int gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
flcn->is_interrupt_enabled = false;
break;
case FALCON_ID_NVDEC:
flcn->flcn_base = FALCON_NVDEC_BASE;
flcn->flcn_base = g->ops.nvdec.falcon_base_addr();
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = true;
break;

2
drivers/gpu/nvgpu/common/falcon/falcon_tu104.c
View File

@@ -68,7 +68,7 @@ int tu104_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
flcn->is_interrupt_enabled = true;
break;
case FALCON_ID_NVDEC:
flcn->flcn_base = pnvdec_falcon_irqsset_r(0);
flcn->flcn_base = g->ops.nvdec.falcon_base_addr();
flcn->is_falcon_supported = true;
flcn->is_interrupt_enabled = true;
break;

30
drivers/gpu/nvgpu/common/nvdec/nvdec_gp106.c Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvdec_gp106.h"
#include <nvgpu/hw/gp106/hw_pnvdec_gp106.h>
u32 gp106_nvdec_falcon_base_addr(void)
{
return pnvdec_falcon_irqsset_r();
}

30
drivers/gpu/nvgpu/common/nvdec/nvdec_gp106.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NVDEC_GP106_H
#define NVGPU_NVDEC_GP106_H
#include <nvgpu/types.h>
u32 gp106_nvdec_falcon_base_addr(void);
#endif /* NVGPU_NVDEC_GP106_H */

30
drivers/gpu/nvgpu/common/nvdec/nvdec_tu104.c Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvdec_tu104.h"
#include <nvgpu/hw/tu104/hw_pnvdec_tu104.h>
u32 tu104_nvdec_falcon_base_addr(void)
{
return pnvdec_falcon_irqsset_r(0);
}

30
drivers/gpu/nvgpu/common/nvdec/nvdec_tu104.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NVDEC_TU104_H
#define NVGPU_NVDEC_TU104_H
#include <nvgpu/types.h>
u32 tu104_nvdec_falcon_base_addr(void);
#endif /* NVGPU_NVDEC_TU104_H */

5
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -54,6 +54,7 @@
#include "common/pmu/acr_gp106.h"
#include "common/falcon/falcon_gk20a.h"
#include "common/falcon/falcon_gp106.h"
#include "common/nvdec/nvdec_gp106.h"
#include "pmu_perf/pmu_perf.h"
#include "gk20a/fifo_gk20a.h"
@@ -511,6 +512,9 @@ static const struct gpu_ops gp106_ops = {
.mem_unlock = NULL,
.get_vidmem_size = gp106_fb_get_vidmem_size,
},
.nvdec = {
.falcon_base_addr = gp106_nvdec_falcon_base_addr,
},
.clock_gating = {
.slcg_bus_load_gating_prod =
gp106_slcg_bus_load_gating_prod,
@@ -928,6 +932,7 @@ int gp106_init_hal(struct gk20a *g)
gops->gr = gp106_ops.gr;
gops->gr.ctxsw_prog = gp106_ops.gr.ctxsw_prog;
gops->fb = gp106_ops.fb;
gops->nvdec = gp106_ops.nvdec;
gops->clock_gating = gp106_ops.clock_gating;
gops->fifo = gp106_ops.fifo;
gops->netlist = gp106_ops.netlist;

5
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -66,6 +66,7 @@
#include "common/falcon/falcon_gk20a.h"
#include "common/falcon/falcon_gp106.h"
#include "common/falcon/falcon_gv100.h"
#include "common/nvdec/nvdec_gp106.h"
#include "pmu_perf/perf_gv100.h"
#include "gk20a/fifo_gk20a.h"
@@ -630,6 +631,9 @@ static const struct gpu_ops gv100_ops = {
.fault_buf_configure_hw = gv11b_fb_fault_buf_configure_hw,
.get_vidmem_size = gv100_fb_get_vidmem_size,
},
.nvdec = {
.falcon_base_addr = gp106_nvdec_falcon_base_addr,
},
.clock_gating = {
.slcg_bus_load_gating_prod =
gv100_slcg_bus_load_gating_prod,
@@ -1092,6 +1096,7 @@ int gv100_init_hal(struct gk20a *g)
gops->gr = gv100_ops.gr;
gops->gr.ctxsw_prog = gv100_ops.gr.ctxsw_prog;
gops->fb = gv100_ops.fb;
gops->nvdec = gv100_ops.nvdec;
gops->clock_gating = gv100_ops.clock_gating;
gops->fifo = gv100_ops.fifo;
gops->netlist = gv100_ops.netlist;

1
drivers/gpu/nvgpu/include/nvgpu/falcon.h
View File

@@ -42,7 +42,6 @@
/*
* Falcon Base address Defines
*/
#define FALCON_NVDEC_BASE 0x00084000U
#define FALCON_PWR_BASE 0x0010a000U
#define FALCON_SEC_BASE 0x00087000U
#define FALCON_FECS_BASE 0x00409000U

3
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -697,6 +697,9 @@ struct gpu_ops {
size_t (*get_vidmem_size)(struct gk20a *g);
int (*apply_pdb_cache_war)(struct gk20a *g);
} fb;
struct {
u32 (*falcon_base_addr)(void);
} nvdec;
struct {
void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod);
void (*slcg_ce2_load_gating_prod)(struct gk20a *g, bool prod);

5
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -72,6 +72,7 @@
#include "common/falcon/falcon_gp106.h"
#include "common/falcon/falcon_gv100.h"
#include "common/falcon/falcon_tu104.h"
#include "common/nvdec/nvdec_tu104.h"
#include "gk20a/fifo_gk20a.h"
#include "gk20a/fecs_trace_gk20a.h"
@@ -658,6 +659,9 @@ static const struct gpu_ops tu104_ops = {
.get_vidmem_size = gv100_fb_get_vidmem_size,
.apply_pdb_cache_war = tu104_fb_apply_pdb_cache_war,
},
.nvdec = {
.falcon_base_addr = tu104_nvdec_falcon_base_addr,
},
.clock_gating = {
.slcg_bus_load_gating_prod =
tu104_slcg_bus_load_gating_prod,
@@ -1118,6 +1122,7 @@ int tu104_init_hal(struct gk20a *g)
gops->gr = tu104_ops.gr;
gops->gr.ctxsw_prog = tu104_ops.gr.ctxsw_prog;
gops->fb = tu104_ops.fb;
gops->nvdec = tu104_ops.nvdec;
gops->clock_gating = tu104_ops.clock_gating;
gops->fifo = tu104_ops.fifo;
gops->netlist = tu104_ops.netlist;