gpu: nvgpu: update hw headers with falcon IRQSSET & IRQSCLR

For gk20a & gp106, nvgpu driver currently hardcodes base address for FECS,
GPCCS, NVDEC falcons. Instead, emit those register in the hw headers. Base
address is the address of IRQSSET register.

JIRA NVGPU-1587

Change-Id: I710c4006b5ef6ded7980491ac157f8c03399b831
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966643
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h

@@ -842,10 +842,26 @@ static inline u32 gr_fecs_bootvec_vec_f(u32 v)
 {
 	return (v & 0xffffffffU) << 0U;
 }
+static inline u32 gr_fecs_irqsset_r(void)
+{
+	return 0x00409000U;
+}
+static inline u32 gr_fecs_irqsclear_r(void)
+{
+	return 0x00409004U;
+}
 static inline u32 gr_fecs_falcon_hwcfg_r(void)
 {
 	return 0x00409108U;
 }
+static inline u32 gr_gpcs_gpccs_irqsset_r(void)
+{
+	return 0x0041a000U;
+}
+static inline u32 gr_gpcs_gpccs_irqsclr_r(void)
+{
+	return 0x0041a004U;
+}
 static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
 {
 	return 0x0041a108U;

drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h

@@ -986,10 +986,26 @@ static inline u32 gr_fecs_bootvec_vec_f(u32 v)
 {
 	return (v & 0xffffffffU) << 0U;
 }
+static inline u32 gr_fecs_irqsset_r(void)
+{
+	return 0x00409000U;
+}
+static inline u32 gr_fecs_irqsclr_r(void)
+{
+	return 0x00409004U;
+}
 static inline u32 gr_fecs_falcon_hwcfg_r(void)
 {
 	return 0x00409108U;
 }
+static inline u32 gr_gpcs_gpccs_irqsset_r(void)
+{
+	return 0x0041a000U;
+}
+static inline u32 gr_gpcs_gpccs_irqsclr_r(void)
+{
+	return 0x0041a004U;
+}
 static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
 {
 	return 0x0041a108U;

drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pnvdec_gp106.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef NVGPU_HW_PNVDEC_GP106_H
+#define NVGPU_HW_PNVDEC_GP106_H
+
+#include <nvgpu/types.h>
+
+static inline u32 pnvdec_falcon_irqsset_r(void)
+{
+	return 0x00084000U;
+}
+static inline u32 pnvdec_falcon_irqsclr_r(void)
+{
+	return 0x00084004U;
+}
+#endif