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8 Commits

Author SHA1 Message Date
Seema Khowala
b4ec1c5dff gpu: nvgpu: move dump_channel_status from fifo to channel 
Renamed and moved from fifo to channel
gk20a_debug_dump_all_channel_status_ramfc -> nvgpu_channel_debug_dump_all
gk20a_dump_channel_status_ramfc -> gk20a_channel_debug_dump
gv11b_dump_channel_status_ramfc -> gv11b_channel_debug_dump

Moved nvgpu_channel_dump_info struct to channel.h
Moved nvgpu_channel_hw_state struct to channel.h
Moved dump_channel_status_ramfc fifo ops to channel ops
as debug_dump

JIRA NVGPU-2978

Change-Id: I696e5029d9e6ca4dc3516651b4d4f5230fe8b0b0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2092709
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-10 16:15:50 -07:00
Seema Khowala
fe2a599700 gpu: nvgpu: rename fifo_eng_timeout_us 
Rename fifo_eng_timeout_us to ctxsw_timeout_period_ms for
clarity.

JIRA NVGPU-1312

Change-Id: I23faff3df7160c1193f797ac03769ef2ecf4449e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076776
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-03-25 22:47:09 -07:00
Seema Khowala
f66f3e1341 gpu: nvgpu: move fifo intr to hal/fifo 
Removed intr_0_error_mask ops

Added below ops for fifo intr
intr_0_enable
intr_1_enable
intr_0_isr
intr_1_isr

JIRA NVGPU-1310

Change-Id: I19bd1a380a89cffd582d6c4a0b7796a46fec5afb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072144
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-03-25 11:03:39 -07:00
Thomas Fleury
6729d67f59 gpu: nvgpu: vpgu: use fifo common init/deinit code 
Native and vgpu were using different paths for fifo
init/deinit code.

Use same nvgpu_fifo_init_support for init code:

nvgpu_fifo_init_support
  g->ops.fifo.setup_sw
    vgpu_fifo_setup_sw (NEW)

Use same nvgpu_fifo_remove_support for deinit code:

nvgpu_fifo_remove_support (NEW)
  g->ops.fifo.cleanup_sw (NEW)
    vgpu_fifo_cleanup_sw (NEW)

Also implemented gk20a_fifo_cleanup_sw for native case.

Jira NVGPU-1306
Jira NVGPU-2855

Change-Id: Iefe303cc224f804a206422e2efffda9da1616d89
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029649
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-03-18 16:56:04 -07:00
Thomas Fleury
ffed5095db gpu: nvgpu: move fifo init/deinit code to common 
Add fifo sub-unit to common.fifo to handle init/deinit code
and global support functions.

Split init into:
- nvgpu_channel_setup_sw
- nvgpu_tsg_setup_sw
- nvgpu_fifo_setup_sw
- nvgpu_runlist_setup_sw
- nvgpu_engine_setup_sw
- nvgpu_userd_setup_sw
- nvgpu_pbdma_setup_sw

Split de-init into
- nvgpu_channel_cleanup_sw
- nvgpu_tsg_cleanup_sw
- nvgpu_fifo_cleanup_sw
- nvgpu_runlist_cleanup_sw
- nvgpu_engine_cleanup_sw
- nvgpu_userd_cleanup_sw
- nvgpu_pbdma_cleanup_sw

Added the following HALs
- runlist.length_max
- fifo.init_pbdma_info
- fifo.userd_entry_size

Last 2 HALs should be moved resp. to pbdma and userd sub-units,
when available.

Added vgpu implementation of above hals
- vgpu_runlist_length_max
- vgpu_userd_entry_size
- vgpu_channel_count

Use hals in vgpu_fifo_setup_sw.

Jira NVGPU-1306

Change-Id: I954f56be724eee280d7b5f171b1790d33c810470
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029620
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-03-14 20:35:22 -07:00
Konsta Holtta
9457a5ea91 gpu: nvgpu: add eng_faulted to channel HAL for gv11b+ 
The ccsr_channel_eng_faulted field exists from Volta onwards. Implement
the read_state HAL op for those chips, and store that bit as a boolean
in the channel state info.

Jira NVGPU-1307

Change-Id: Ie997892f2d3db0725496661a4d3083e7396894cc
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017267
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-02-12 17:06:18 -08:00
Konsta Holtta
cd4b2f642c gpu: nvgpu: add HAL for reading ccsr_channel 
Refactor read accesses to the ccsr_channel register for channel state to
be done via a channel HAL op for all chips. A new op called read_state
is added for this; information needed by other units is collected in a
new struct nvgpu_channel_hw_state.

Jira NVGPU-1307

Change-Id: Iff9385c08e17ac086d97f5771a54b56b2727e3c4
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017266
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-02-12 17:06:09 -08:00
Debarshi Dutta
ac4c2d4ae0 gpu: nvgpu: move fifo RC_TYPE_* definitions to common header 
The RC_TYPE_* definitions in fifo_gk20a.h are generic and are moved to
a newly constructed common header <nvgpu/fifo.h>

Jira NVGPU-1237

Change-Id: Ia1bb80b9b0047675c7abfb6ce6ccd42a2e99f41f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1970031
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2018-12-14 21:54:39 -08:00