* Updated types and added error checks
* Modified GR condition for ctxsw disable count
CERT-C error check was added to detect error on integer overflow
But below logic couldn't detect first overflow, so updated condition
INT_MAX < gr->ctxsw_disable_count --> it became true after overflow
So, we didn't detected in first overflow and lead to assert on enable
JIRA NVGPU-3400
Change-Id: I6b0265a464f8f19efa7b0761612c6e9ffb3bd2bd
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2206282
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-Renamed ACR structs for FUSA, ACR FUSA code has struct names
ending with _v1 & ACR non-FUSA with _v0, removed _v1 for FUSA
code to keep struct without any versioning for doxygen.
-Renamed acr_blob_construct_v1.c/h to acr_blob_construct.c/h
JIRA NVGPU-2516
Change-Id: Id2d5e48e8169ce59371c2b08d04c5a65ba94c685
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2218265
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ACR HS ucode is currently loaded by pmu_bl.bin (falcon bootloader),
but ACR ucode can be loaded without bootloader support by directly
copying non-secure/secure code to respective IMEM offset along with
required data to DMEM, with this bootloader dependency is removed.
This patch uses nvgpu_acr_self_hs_load_bootstrap to directly load
acr ucode to imem using priv writes. This also removes the bootloader
related code
JIRA NVGPU-3811
Change-Id: Ie2632eb26e421de3765a99c5426471eb37bf1bc9
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2169976
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void.
The ACR operations acr_fill_bl_dmem_desc and patch_wpr_info_to_ucode
were returning an int that was always 0. This patch changes their
signature to return void instead.
JIRA NVGPU-3032
Change-Id: I4116db3b5aec92ee9b914f5549d6c7c994affd4a
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090042
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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ACR WPR/blob-alloc functions are called from different parts of
ACR UNIT like bootstrap, blob-construct & chip specific ACR sw
init functions, these functions are part of acr.c which adds
circular dependency between acr.c & other files, so, moved to
respective new fiels based on its operation & also cleaned up
header dependency.
JIRA NVGPU-2907
Change-Id: I78d1eab59757029017d6ca62cbfc227a7a8240e4
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081632
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As part of ACR bootstrap, falcon bootstrap request is sent to engine HAL
functions along with bootloader structure & perform falcon boot, but
this adds constraint to HAL separation due to struct parameter, so
made ACR to handle falcon boot by using falcon interfaces along with
new HAL ops to setup engine falcon setup. This also helps to reduce
code duplication too.
JIRA NVGPU-2039
Change-Id: I6ca29390b74d75bad0467a3c17623a395ec9bc25
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072940
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Currently ACR header files are part of "include/nvgpu/acr/" folder &
ACR interfaces are not used by any other UNIT which allows headers to
keep restricted to ACR unit, as ACR can be divided into two stage
process like blob preparation & bootstrap, so moved header files from
of "include/nvgpu/acr/" to "nvgpu/common/acr/" to respective blob/
bootstrap/acr header files along with its dependent interfaces, this
allows interfaces restricted to header file based on operation it does.
With this any access to ACR must go through provided public functions,
this header move change caused large code modification & required to
make it with big single CL to avoid build break.
JIRA NVGPU-2907
Change-Id: Idb24b17a35f7c7a85efe923c4e26edfd42b028e3
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2071393
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
