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gpu: nvgpu: Add ACR-FUSA support

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-Changes to support ACR AHESASC/ASB ucode HS signature verification
 for FUSA
-Load FUSA/NON_FUSA algorithm based ucodes using flag is_fusa_sku
 which will be based on pcie devid
-New defines for AHESESC/ASB FUSA ACR types

JIRA NVGPU-3727

Change-Id: Iedfc069dd540b9593207a4bf7152049957e0dc78
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2161164
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2019-07-25 15:47:15 +05:30
committed by mobile promotions
parent 6290d92926
commit 01dc65fe32
3 changed files with 79 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/common/acr/acr_bootstrap.h
View File

@@ -162,9 +162,11 @@ struct acr_fw_header {
/* ACR Falcon descriptor's */
struct hs_acr {
#define ACR_DEFAULT 0U
#define ACR_AHESASC 1U
#define ACR_ASB 2U
#define ACR_DEFAULT 0U
#define ACR_AHESASC_NON_FUSA 1U
#define ACR_ASB_NON_FUSA 2U
#define ACR_AHESASC_FUSA 3U
#define ACR_ASB_FUSA 4U
u32 acr_type;
/* HS bootloader to validate & load ACR ucode */

13
drivers/gpu/nvgpu/common/acr/acr_priv.h
View File

@@ -73,10 +73,15 @@ struct wpr_carveout_info;
#define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin"
#define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin"
#define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin"
#define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin"
#define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin"
#define HSBIN_ACR_ASB_DBG_UCODE "acr_asb_dbg_ucode.bin"
#define HSBIN_ACR_AHESASC_NON_FUSA_PROD_UCODE "acr_ahesasc_prod_ucode.bin"
#define HSBIN_ACR_ASB_NON_FUSA_PROD_UCODE "acr_asb_prod_ucode.bin"
#define HSBIN_ACR_AHESASC_NON_FUSA_DBG_UCODE "acr_ahesasc_dbg_ucode.bin"
#define HSBIN_ACR_ASB_NON_FUSA_DBG_UCODE "acr_asb_dbg_ucode.bin"
#define HSBIN_ACR_AHESASC_FUSA_PROD_UCODE "acr_ahesasc_fusa_prod_ucode.bin"
#define HSBIN_ACR_ASB_FUSA_PROD_UCODE "acr_asb_fusa_prod_ucode.bin"
#define HSBIN_ACR_AHESASC_FUSA_DBG_UCODE "acr_ahesasc_fusa_dbg_ucode.bin"
#define HSBIN_ACR_ASB_FUSA_DBG_UCODE "acr_asb_fusa_dbg_ucode.bin"
#define GM20B_FECS_UCODE_SIG "fecs_sig.bin"
#define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin"

79
drivers/gpu/nvgpu/common/acr/acr_sw_tu104.c
View File

@@ -70,20 +70,49 @@ static u32 tu104_acr_lsf_sec2(struct gk20a *g,
return BIT32(lsf->falcon_id);
}
/* fusa signing enable check */
static bool tu104_acr_is_fusa_enabled(struct gk20a *g)
{
return g->is_fusa_sku;
}
/* ACR-AHESASC(ACR hub encryption setter and signature checker) init*/
static void nvgpu_tu104_acr_ahesasc_sw_init(struct gk20a *g,
static void tu104_acr_ahesasc_non_fusa_ucode_select(struct gk20a *g,
struct hs_acr *acr_ahesasc)
{
acr_ahesasc->acr_type = ACR_AHESASC_NON_FUSA;
if (!g->ops.pmu.is_debug_mode_enabled(g)) {
acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_NON_FUSA_PROD_UCODE;
} else {
acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_NON_FUSA_DBG_UCODE;
}
}
static void tu104_acr_ahesasc_fusa_ucode_select(struct gk20a *g,
struct hs_acr *acr_ahesasc)
{
acr_ahesasc->acr_type = ACR_AHESASC_FUSA;
if (!g->ops.pmu.is_debug_mode_enabled(g)) {
acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_FUSA_PROD_UCODE;
} else {
acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_FUSA_DBG_UCODE;
}
}
static void tu104_acr_ahesasc_sw_init(struct gk20a *g,
struct hs_acr *acr_ahesasc)
{
struct hs_flcn_bl *hs_bl = &acr_ahesasc->acr_hs_bl;
hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
acr_ahesasc->acr_type = ACR_AHESASC;
if (!g->ops.pmu.is_debug_mode_enabled(g)) {
acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_PROD_UCODE;
if (tu104_acr_is_fusa_enabled(g)) {
tu104_acr_ahesasc_fusa_ucode_select(g, acr_ahesasc);
} else {
acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_DBG_UCODE;
tu104_acr_ahesasc_non_fusa_ucode_select(g, acr_ahesasc);
}
acr_ahesasc->ptr_bl_dmem_desc = &acr_ahesasc->bl_dmem_desc_v1;
@@ -96,19 +125,41 @@ static void nvgpu_tu104_acr_ahesasc_sw_init(struct gk20a *g,
}
/* ACR-ASB(ACR SEC2 booter) init*/
static void nvgpu_tu104_acr_asb_sw_init(struct gk20a *g,
static void tu104_acr_asb_non_fusa_ucode_select(struct gk20a *g,
struct hs_acr *acr_asb)
{
acr_asb->acr_type = ACR_ASB_NON_FUSA;
if (!g->ops.pmu.is_debug_mode_enabled(g)) {
acr_asb->acr_fw_name = HSBIN_ACR_ASB_NON_FUSA_PROD_UCODE;
} else {
acr_asb->acr_fw_name = HSBIN_ACR_ASB_NON_FUSA_DBG_UCODE;
}
}
static void tu104_acr_asb_fusa_ucode_select(struct gk20a *g,
struct hs_acr *acr_asb)
{
acr_asb->acr_type = ACR_ASB_FUSA;
if (!g->ops.pmu.is_debug_mode_enabled(g)) {
acr_asb->acr_fw_name = HSBIN_ACR_ASB_FUSA_PROD_UCODE;
} else {
acr_asb->acr_fw_name = HSBIN_ACR_ASB_FUSA_DBG_UCODE;
}
}
static void tu104_acr_asb_sw_init(struct gk20a *g,
struct hs_acr *acr_asb)
{
struct hs_flcn_bl *hs_bl = &acr_asb->acr_hs_bl;
hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
acr_asb->acr_type = ACR_ASB;
if (!g->ops.pmu.is_debug_mode_enabled(g)) {
acr_asb->acr_fw_name = HSBIN_ACR_ASB_PROD_UCODE;
if (tu104_acr_is_fusa_enabled(g)) {
tu104_acr_asb_fusa_ucode_select(g, acr_asb);
} else {
acr_asb->acr_fw_name = HSBIN_ACR_ASB_DBG_UCODE;
tu104_acr_asb_non_fusa_ucode_select(g, acr_asb);
}
acr_asb->ptr_bl_dmem_desc = &acr_asb->bl_dmem_desc_v1;
@@ -134,8 +185,8 @@ void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
acr->bootstrap_hs_acr = tu104_bootstrap_hs_acr;
/* Init ACR-AHESASC */
nvgpu_tu104_acr_ahesasc_sw_init(g, &acr->acr_ahesasc);
tu104_acr_ahesasc_sw_init(g, &acr->acr_ahesasc);
/* Init ACR-ASB*/
nvgpu_tu104_acr_asb_sw_init(g, &acr->acr_asb);
tu104_acr_asb_sw_init(g, &acr->acr_asb);
}