Commit Graph

19 Commits

Author SHA1 Message Date
Deepak Nibade
b3f575074b gpu: nvgpu: fix sparse warnings
Fix below sparse warnings :

warning: Using plain integer as NULL pointer
warning: symbol <variable/funcion> was not declared. Should it be static?
warning: Initializer entry defined twice

Also, remove dead functions

Bug 1573254

Change-Id: I29d71ecc01c841233cf6b26c9088ca8874773469
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/593363
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2015-03-18 12:12:01 -07:00
sujeet baranwal
5febd08ae7 gpu: kernel support for suspending/resuming SMs
Kernel support for allowing a GPU debugger to suspend and resume
SMs. Invocation of "suspend" on a given channel will suspend all
SMs if the channel is resident, else remove the channel form the
runlist. Similarly, "resume" will either resume all SMs if the
channel was resident, or re-enable the channel in the runlist.

Change-Id: I3b4ae21dc1b91c1059c828ec6db8125f8a0ce194
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Reviewed-on: http://git-master/r/552115
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:57 -07:00
Mayank Kaushik
1ee103adf3 gpu: nvgpu: create a hal function for smpc war
Create a HAL function for applying the SMPC workaround.The workaround
is only needed on gk20a, and not on gm20b.

Change-Id: I9edc741df32ab7d1dad38ecc56f238828128bfef
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Reviewed-on: http://git-master/r/539187
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:57 -07:00
Konsta Holtta
2d0bcfa331 gpu: nvgpu: add __must_check to gk20a_busy
The return value of gk20a_busy must be checked since it may not succeed
in some cases. Add the __must_check attribute that generates a compiler
warning for code that does not read the return value and fix all uses of
the function to take error cases into account.

Bug 200040921

Change-Id: Ibc2b119985fa230324c88026fe94fc5f1894fe4f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542552
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:34 -07:00
Konsta Holtta
28476a5b13 gpu: nvgpu: create new nvgpu ioctl header
Move nvgpu ioctls from the many user space interface headers to a new
single nvgpu.h header under include/uapi. No new code or replaced names
are introduced; this change only moves the definitions and changes
include directives accordingly.

Bug 1434573

Change-Id: I4d02415148e437a4e3edad221e08785fac377e91
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542651
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:33 -07:00
Konsta Holtta
719923ad9f gpu: nvgpu: rename gpu ioctls and structs to nvgpu
To help remove the nvhost dependency from nvgpu, rename ioctl defines
and structures used by nvgpu such that nvhost is replaced by nvgpu.
Duplicate some structures as needed.

Update header guards and such accordingly.

Change-Id: Ifc3a867713072bae70256502735583ab38381877
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542620
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:33 -07:00
Konsta Holtta
6b85e32d6c gpu: nvgpu: fix -EINVAL retval in ioctls
Proper error number for invalid request number is EINVAL instead of
EFAULT, so change it in ioctl calls.

Change-Id: I8fddd34e012700550e9e30fe17ba7152b3a0417b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542563
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:31 -07:00
Terje Bergstrom
b05d85a29d gpu: nvgpu: Change error for invalid ioctl to dbg
Change loglevel of text for invalid ioctl to dbg.

Bug 20038780

Change-Id: I0a2ba97d9c21b2225f8d3db59c80b70c2f2c679e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/501171
GVS: Gerrit_Virtual_Submit
2015-03-18 12:11:23 -07:00
Terje Bergstrom
8be2f2bf4c gpu: nvgpu: gm20b: Regenerate clock gating lists
Regenerate clock gating lists. Add new blocks, and takes them into
use. Also moves some clock gating settings to be applied at the
earliest possible moment right after reset.

Change-Id: I21888186c200f7a477c63bd3332e8ed578f63741
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/457698
2015-03-18 12:11:09 -07:00
Terje Bergstrom
e2638d73fd gpu: nvgpu: Wait for idle via FIFO registers
Wait for engine idle via FIFO's engine status instead of submitting
WFI to channel. Submitting WFI and waiting is not robust, and wait
might invoke debug dump which cannot be done while powering down.

Bug 1499214

Change-Id: I4d52e8558e1a862ad4292036594d81ebfbd5f36b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/432151
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
2015-03-18 12:10:20 -07:00
Vijayakumar
88c6d2fb21 gpu:nvgpu:fix powergate disabling order
ELPG has to disabled before we write to clock gating registers
If ELPG is engaged during clock gating register write it will
cause error in ELPG engine

Bug 200013495
Bug 200014542

Change-Id: I57d1c59fc9311686829d898faddc90149df4cb46
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/432117
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
2015-03-18 12:10:19 -07:00
Deepak Nibade
ccbe6c44d3 gpu: nvgpu: fix memory leak of dbg_session
In gk20a_dbg_gpu_dev_release() (when we close nvhost-dgb-gpu sysfs),
we return from function if there is no channel bound to dbg_session
without freeing the dbg_session memory.

If there is no channel bound then do not call dbg_unbind_channel_gk20a()
and then free dbg_session memory always.

Bug 200010382

Change-Id: I90dd2ed3cd72fbc5d429799660daf2a09b974fda
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/419306
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:05 -07:00
Terje Bergstrom
66bb831f44 gpu: nvgpu: Register as subdomain of host1x
Add gk20a as a sub power domain of host1x. This enforces keeping
host1x on when using gk20a.

Bug 200003112

Change-Id: I08db595bc7b819d86d33fb98af0d8fb4de369463
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/407006
(cherry picked from commit 009812b3e510518740e9c7e89b8b8b80439fe26a)
Reviewed-on: http://git-master/r/408013
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:48 -07:00
Matt Pedro
6c6936858a Revert "gpu: nvgpu: Keep host1x on when GPU on"
This reverts commit 20d48a759b032116e3092e1df76518065da59879.

Change-Id: I93718a314b70ee9284a83ca69964883e670ad78d
Signed-off-by: Matt Pedro <mapedro@nvidia.com>
Reviewed-on: http://git-master/r/407969
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:48 -07:00
Sandarbh Jain
ebe7f110a1 gpu: nvgpu: gk20a: Control powergating on regops
Enable/disable powergating around regops so that the user
need not call the powergating IOCTLs with the regops IOCTL.
If the user does call the powergating IOCTL then the ref-counting
will ensure the correct behavior.

Bug 1451949

Change-Id: I1746f7d7cd1d2c0c497c213939df44a59d5d2834
Signed-off-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-on: http://git-master/r/395131
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:47 -07:00
Kevin Huang
09f1bebcd5 gpu: nvgpu: fix memory leak in regops ioctl
Bug 200003921

Change-Id: Iebaca62793201ae86ce5f2cf4af3fc870a2aa3a6
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/408415
(cherry picked from commit 7d8fd07a26e33ba53a71dae475dc1074d52767a8)
Signed-off-by: Hridya <hvalsaraju@nvidia.com>
Reviewed-on: http://git-master/r/409832
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alka Mohite <amohite@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Tested-by: Deepak Nibade <dnibade@nvidia.com>
2015-03-18 12:09:21 -07:00
Terje Bergstrom
4ac110cb8a gpu: nvgpu: Register as subdomain of host1x
Add gk20a as a sub power domain of host1x. This enforces keeping
host1x on when using gk20a.

Bug 200003112

Change-Id: I08db595bc7b819d86d33fb98af0d8fb4de369463
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/407543
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
2015-03-18 12:09:20 -07:00
Kerwin Wan
875d12c7a0 gpu: nvgpu: gk20a: check the return value of gk20a_channel_busy
gk20a_channel_busy is called to host gpu so that gk20a can be accessed.
But it may return error like if gpu fails to be powered on. Always check
the return value of gk20a_channel_busy to avoid illegal access to gk20a.

Bug 1488409

Change-Id: Ie22da9e436ee5ea711003530419f546a73791b73
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/395180
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:09:11 -07:00
Arto Merilainen
a9785995d5 gpu: nvgpu: Add NVIDIA GPU Driver
This patch moves the NVIDIA GPU driver to a new location.

Bug 1482562

Change-Id: I24293810b9d0f1504fd9be00135e21dad656ccb6
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/383722
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:08:53 -07:00