Commit Graph

385 Commits

Author SHA1 Message Date
Richard Zhao
dcff39ba8c gpu: nvgpu: vgpu: set detach_snapshot in gv11b gops
It has to be set to detach snapshot. We missed it somehow.

Jira VFND-4703

Change-Id: Ia5842494f86fb2d788d72ba372ee8870977a2f67
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640668
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-01-24 14:41:41 -08:00
Inamdar Sharif
6a5bd72856 Revert "Revert "gpu: nvgpu: disable_syncpoints debugfs changed to read only""
This reverts commit 4021d42cbb.
Original change was reverted since that was suspected to have caused
opengles test faulure on QNX, but it turned out that the original change
was actually not causing the failure. Hence original change is restored.

Change-Id: I64796f1a3b1f700f294c259d4426c493f2f1ad85
Signed-off-by: Inamdar Sharif <isharif@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1643309
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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2018-01-24 02:00:04 -08:00
Konsta Holtta
1b75e7277a Revert "gpu: nvgpu: gv11b: enable devfreq"
This reverts commit 968d8cd3e5.

Bug 2049965

Bug 2039013
Bug 200377508

Change-Id: I813947417740f8d3a0c9bea82784df1dd4a5f1ac
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644224
Reviewed-by: David Pu <dpu@nvidia.com>
Tested-by: David Pu <dpu@nvidia.com>
2018-01-23 09:31:56 -08:00
Terje Bergstrom
f3f14cdff5 gpu: nvgpu: Fold T19x code back to main code paths
Lots of code paths were split to T19x specific code paths and structs
due to split repository. Now that repositories are merged, fold all of
them back to main code paths and structs and remove the T19x specific
Kconfig flag.

Change-Id: Id0d17a5f0610fc0b49f51ab6664e716dc8b222b6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640606
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-01-22 22:20:15 -08:00
seshendra Gadagottu
193a2ed38c gpu: nvgpu: add sw method for SET_BES_CROP_DEBUG4
Added sw method support for SET_BES_CROP_DEBUG4.
In this sw method:
CLAMP_FP_BLEND_TO_MAXVAL forces overflow and
CLAMP_FP_BLEND_TO_INF blend results to clamp to FP maxval.

Added support for this sw method in gp10b/gp106/gv11b
and gv100.

Bug 2046636

Change-Id: I3a9e97587aca76718f7f504ea3b853f87409092a
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1641529
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2018-01-22 15:29:54 -08:00
Konsta Holtta
3ccf5c85fb gpu: nvgpu: add g->sw_ready flag
Fix a race condition where we'd still be booting up the gpu and/or
initializing the driver but elsewhere assume that all is done already.

Some userspace APIs to make sure that we're ready by testing
g->gr.sw_ready, but this flag is set in the middle of bootup; there are
other things after gr initialization. Add a new flag that is enabled
after bootup is fully complete at the end of finalize_poweron, and
change the checks in user API paths to test the new flag only.

These checks are only in the ioctl paths for ctrl, dbg and tsg, and in
the ctrl device's opening path.

The gr.sw_ready flag is still left there to signify whether just gr has
had its bookkeeping initialized.

Bug 200370011

Change-Id: I2995500e06de46430d9b835de1e9d60b3f01744e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640124
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2018-01-20 02:19:02 -08:00
Inamdar Sharif
4021d42cbb Revert "gpu: nvgpu: disable_syncpoints debugfs changed to read only"
This reverts commit c713934675.
since this change is causing ap_opengles_screen to fail on
embedded-qnx-hv

Change-Id: I812d3483df961def492fb49c14911f6bcca36da4
Signed-off-by: Inamdar Sharif <isharif@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1642759
2018-01-20 00:25:06 -08:00
Seema Khowala
c713934675 gpu: nvgpu: disable_syncpoints debugfs changed to read only
Syncpoints can longer be disabled/enabled during run time as
NVGPU_HAS_SYNCPOINTS flag is set based on has_syncpoints
value in platform data during probe. Based on this, either
of syncpoint or semaphore pool is initialized.

Bug 2040115

Change-Id: Ib256e1a6ec8b1584799adb6f183fd567aebfaf13
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640380
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2018-01-19 13:59:16 -08:00
seshendra Gadagottu
968d8cd3e5 gpu: nvgpu: gv11b: enable devfreq
Enable devfreq for gv11b by enabling ""nvhost_podgov"
governor in platform data.

Reuse scaling functions from gp10b/gk20a.

Remove emc floor on railgate for power saving and make
max emc frequency as floor in rail-ungate for faster gpu boot.

Bug 2039013
Bug 200377508

Change-Id: I65ee7735202e3decbe3451157f7fc1f1f273c3ff
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639752
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-01-19 11:39:54 -08:00
Alex Waterman
d52b88315a gpu: nvgpu: fix typo
Rename gb10b_init_bar2_vm*() to gp10b_init_bar2_vm*().

Bug 200378257

Change-Id: I9f8a9ef42c82923200d7053c61bab2652b58cbc2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639757
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2018-01-18 23:40:35 -08:00
Deepak Goyal
e0dbf3a784 gpu: nvgpu: gv11b: Enable perfmon.
t19x PMU ucode uses RPC mechanism for
PERFMON commands.

- Declared  "pmu_init_perfmon",
  "pmu_perfmon_start_sampling",
  "pmu_perfmon_stop_sampling" and
  "pmu_perfmon_get_samples" in pmu ops
  to differenciate for chips using RPC & legacy
  cmd/msg mechanism.
- Defined and used PERFMON RPC commands for t19x
  	- INIT
	- START
	- STOP
	- QUERY
- Adds RPC handler for PERFMON RPC commands.
- For guerying GPU utilization/load, we need to send PERFMON_QUERY
  RPC command for gv11b.
- Enables perfmon for gv11b.

Bug 2039013

Change-Id: Ic32326f81d48f11bc772afb8fee2dee6e427a699
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1614114
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2018-01-18 23:40:02 -08:00
Alex Waterman
badfffe3ef gpu: nvgpu: add cleanup in gk20a_probe()
Add cleanup to the gk20a_probe() function since it will often fail
due to probe deferal. These "failures" cause this function to be
called multiple times and potentially allocate many resources over
and over again, leaking the old allocations.

Bug 200369627

Change-Id: Ic0bba0ae6542485135d9cb7393086e4460cd271d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640628
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2018-01-18 18:10:18 -08:00
seshendra Gadagottu
ea9cb56cf6 gpu: nvgpu: railgate platform only if it is not railgated
Avoid railgating platform, if it is already in railgated state.
This is right thing to do and it also avoids ref counting issues
related to fuse clock disable.

Bug 200381275

Change-Id: Id745f9b878be129bf9b0cc972fadcfc102c8ddc2
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640548
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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2018-01-18 18:10:08 -08:00
Seema Khowala
2deab755e7 gpu: nvgpu: bypass_smmu debugfs changed to read only
bypass_smmu is set based on whether device_is_iommuable
or not during probe. It cannot be changed during runtime.

Change-Id: I69fd29c87ea3873652a4eb95764f52dc40abf483
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640381
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2018-01-18 10:30:15 -08:00
Terje Bergstrom
2f6698b863 gpu: nvgpu: Make graphics context property of TSG
Move graphics context ownership to TSG instead of channel. Combine
channel_ctx_gk20a and gr_ctx_desc to one structure, because the split
between them was arbitrary. Move context header to be property of
channel.

Bug 1842197

Change-Id: I410e3262f80b318d8528bcbec270b63a2d8d2ff9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639532
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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2018-01-17 12:29:09 -08:00
Aparna Das
47c794ab52 gpu: nvgpu: vgpu: add l3 allocation support
Modify rpc command parameter to support l3 cache
allocation.

Jira EVLR-1752

Change-Id: I1be00e04ee01c0763f46c0d0da6a112316cc7e1d
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1616566
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2018-01-12 13:26:41 -08:00
Richard Zhao
9dd3bb2e62 gpu: nvgpu: vgpu: move t19x specific code to general code
- remove vgpu_t19x.h and tegra_vgpu_t19x.h
- merge t19x specific ivc commands to the big enum
- move TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT to constants

Jira EVLR-2293

Change-Id: I34344bffa03bb69e1282b1f19382e3199f9ba105
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1636128
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2018-01-12 12:43:40 -08:00
Terje Bergstrom
ece3d958b3 gpu: nvgpu: Combine gk20a and gp10b free_gr_ctx
gp10b version of free_gr_ctx was created to keep gp10b source code
changes out from the mainline. gp10b was merged back to mainline a
while ago, so this separation is no longer needed. Merge the two
variants.

Change-Id: I954b3b677e98e4248f95641ea22e0def4e583c66
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1635127
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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2018-01-12 12:42:57 -08:00
Terje Bergstrom
44a1208fec gpu: nvgpu: vgpu: Delete gm20b support
Delete gm20b vgpu support. It has not been supported for a long time
and keeping it up-to-date is extra work.

Change-Id: I3c06d29a79cb83d53a25d2242247b4eeabeab310
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1635126
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-01-12 12:42:54 -08:00
Thomas Fleury
6b90684cee gpu: nvgpu: vgpu: get virtual SMs mapping
On gv11b we can have multiple SMs per TPC. Add sm_per_tpc in
vgpu constants to properly dimension the virtual SM to TPC/GPC
mapping in virtualization case.
Use TEGRA_VGPU_CMD_GET_SMS_MAPPING to query current mapping.

Bug 2039676

Change-Id: I817be18f9a28cfb9bd8af207d7d6341a2ec3994b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631203
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2018-01-10 15:57:20 -08:00
Alex Waterman
a30f307554 gpu: nvgpu: Free enabled flags on driver unload
Make sure the enabled flags are freed before the driver unloads.

Bug 200369180

Change-Id: Ibac9ee61ca99bdfda03d76e393c7cd6cb6cc299a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1632752
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2018-01-10 04:05:20 -08:00
David Nieto
6dde9e67d9 gpu: nvgpu: allocate from coherent pool
Maps memory coherently on devices that are connected to a coherent bus.

(1) Add code to be able to get the platform device node.
(2) Create a new flag to mark if the device is connected to a coherent bus
(3) Map memory coherently on coherent devices.

bug 2040331

Change-Id: Ide83a9261acdbbc6e9fef4fc5f38d6f9d0e5ab5b
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1633985
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2018-01-08 14:38:06 -08:00
Seema Khowala
82f253b7c1 gpu: nvgpu: gv11b: init ch_wdt_timeout_ms
This is needed for watchdog to work.

Change-Id: Ic1e197e5f6701fafd8b614cd43bb610bdc8518ae
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1632230
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2018-01-08 14:37:41 -08:00
David Nieto
1f71f475e2 DNI: gpu: nvgpu: Increase GV100 ctxsw timeouts
During bringup and before nvlink is up GV100 on the DDPX platform operates
with a very, very slow sysmem link. In order to get sysmem test to pass
it is neccesary to significantly increase most timeouts by an order the
magnitude.

Bug 2040544

Change-Id: I26858afde4ae80c70f86b47cfff674b6b00b5bf8
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1627417
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2018-01-05 13:54:37 -08:00
Peter Daifuku
de7721ddc9 gpu: nvgpu: no hv support for write_sm_error_state
There is no current need for a virtualized version of
nvgpu_dbg_gpu_ioctl_write_single_sm_error_state, so return
-ENOSYS when virtual.

Bug 200331110

Change-Id: I223a6298eb4c891859f1c8252049f9a83d84ccb5
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631270
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-01-04 11:04:46 -08:00
Terje Bergstrom
dde1913f16 gpu: nvgpu: Do not disable ELPG when committing buffers
Committing buffer addresses only writes to the memory. There's no
need to disable ELPG for the duration, so drop the ELPG protection.

Change-Id: I8d8d08506387197e4737e0311df4a20085496056
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631149
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2018-01-04 11:04:43 -08:00
Deepak Nibade
e0aca109b1 gpu: nvgpu: fix erroneous gk20a_put() call
With a recent rework we moved gk20a_get() call to nvgpu_ioctl_tsg_open(),
but corresponding gk20a_put() call remained in gk20a_tsg_release()

So if a TSG is opened and released from within kernel with APIs
gk20a_tsg_open()/gk20a_tsg_release() we mistakenly drop extra refcount
through gk20a_put()

Fix this by moving gk20a_put() call to nvgpu_ioctl_tsg_release() which
balances gk20a_get() call in nvgpu_ioctl_tsg_open()

Bug 200374011

Change-Id: Id0cec0426e6231309dc530ab5c934dacaba9f8da
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1630969
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2018-01-04 08:46:10 -08:00
Deepak Nibade
292e4a0c6d gpu: nvgpu: return error if TSG allocation fails
In gk20a_cde_load(), if TSG allocation fails we bail out the function without
setting the error code and caller of this functions assumes CDE load is
successful

Fix this by setting explicit error code if TSG allocation fails

Bug 200374011

Change-Id: I6e7bcb325fb0062605fa2f696da4abdeb34e241a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1627117
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2018-01-04 08:45:27 -08:00
Deepak Nibade
e21e253f83 gpu: nvgpu: fix TSG leak from CDE code
In gk20a_cde_remove_ctx(), we unbind the channel from TSG and
close the channel. But we do not drop the TSG refcount leaking
the TSG reference

After allocating sufficient contexts, we see TSG creation fails as below
nvgpu: 17000000.gp10b: gk20a_cde_load:1286 [ERR]  cde: could not create TSG

Fix this by explicitly dropping TSG refcount

Also, do not explicitly unbind the channel from TSG
gk20a_channel_close() will internally unbind the channel from TSG

Bug 200374011

Change-Id: If6d75b20d5e03d710c0597d7a320d1157206a2a5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1627116
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2018-01-04 08:45:11 -08:00
Sami Kiminki
7240b3c251 gpu: nvgpu: Enable secure alloc for GV11b
Kernel needs to be able to allocate VPR memory for buffers for
protected contexts. So, let's call gk20a_tegra_init_secure_alloc
and enable VPR for GV11B.

Bug 2039456
Bug 2040513

Change-Id: Ie27d8f04b1a414c36b42516ce3147d38d8472d54
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1628566
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2018-01-03 01:38:10 -08:00
Terje Bergstrom
86691b59c6 gpu: nvgpu: Remove bare channel scheduling
Remove scheduling IOCTL implementations for bare channels. Also
removes code that constructs bare channels in runlist.

Bug 1842197

Change-Id: I6e833b38e24a2f2c45c7993edf939d365eaf41f0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1627326
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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2018-01-02 13:53:09 -08:00
Terje Bergstrom
14fa8207e2 gpu: nvgpu: Remove TSG required flag
Remove nvgpu internal flag indicating that TSGs are required. We now
require TSGs always. This also fixes a regression where CE channels
were back to using bare channels on gp106.

Bug 1842197

Change-Id: Id359e5a455fb324278636bb8994b583936490ffd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1628481
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2018-01-02 13:53:05 -08:00
Aparna Das
4f67a794dd gpu: nvgpu: vgpu: add io coherency support
Modify command message parameter to support io
coherency.

Jira EVLR-2025

Change-Id: I38b21c72d85f559555c4d97dab73d0f715ecc655
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1614388
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2017-12-30 18:50:40 -08:00
Terje Bergstrom
32353ab744 gpu: nvgpu: Implement abstraction for finding TID
Implement abstraction for finding the thread ID of thread currently
being run. This is tracked for context switch tracing.

In Linux kernel this is implemented by returning PID.

Change-Id: Id46a318894f9a2ff3c85d2c8ef0b02c52783f122
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1627239
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2017-12-28 10:02:09 -08:00
David Nieto
443977daa1 gpu: nvgpu: Add support for GV100 SKU 250
Bug 2040925

Change-Id: Ied06b199fd87411847b9987496c56276f8ebf89c
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1623709
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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2017-12-28 10:01:39 -08:00
David Nieto
8fb6a8562e gpu: nvgpu: gv11b: Report LTC errors per slice
Add support to report ltc ecc errors per slice

(1) use new logic to detect subunits
(2) store size of array and check before comparison to prevent out of bounds
 derefencing
(3) use new hashing to prevent collisions or entries with permuted names

bug 2037425

Change-Id: I63b9f0df43b9dceddc1bae17924c4723072f569e
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1620854
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chris Dragan <kdragan@nvidia.com>
Tested-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
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2017-12-28 10:01:36 -08:00
Terje Bergstrom
f19f22fcc8 gpu: nvgpu: Remove support for channel events
Remove support for events for bare channels. All users have already
moved to TSGs and TSG events.

Bug 1842197

Change-Id: Ib3ff68134ad9515ee761d0f0e19a3150a0b744ab
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1618906
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-12-28 10:01:32 -08:00
Terje Bergstrom
aa52601f62 gpu: nvgpu: Remove support for bare channels
Remove remaining support for bare channels. All users of bare
channels have already moved to TSGs.

Bug 1842197

Change-Id: I1ff12677253b160dac9bebe6925ad0839ea07cfc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1618905
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2017-12-28 10:01:28 -08:00
Supriya
ea1b69d3f5 gpu: nvgpu: Fix crash on read fail of mc_boot_0_r
This CL handles
- erroneous use of boot_0 function pointer
before being assigned in __nvgpu_check_gpu_state
- And proper handling of error returned from gk20a_readl
in gk20a_mc_boot_0
With these fixes crash is not seen in case mc_boot_0 read
returns 0 in gk20a_mc_boot_0
- And also this handles the recursion caused by mc.boot_0()
calling nvgpu_readl and nvgpu_readl in turn
calling mc.boot_0 in case of read failure

Bug 2010966

Change-Id: Ia087811c67d88948b7fc5fff35e0fabc6ea91989
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1616274
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2017-12-28 03:01:48 -08:00
Terje Bergstrom
3a956a573d gpu: nvgpu: Implement abstraction for finding TGID
Implement abstraction for finding the process ID of thread currently
being run. This is tracked for context switch tracing.

In Linux kernel this is implemented by returning TGID.

Change-Id: Ia6bcbd92c8cc25467694a35476e5d5f717194105
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1615985
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2017-12-27 02:21:07 -08:00
Seema Khowala
57a7064ff4 gpu: nvgpu: gv11b: remove cde support
Change-Id: I04df795b20413a2d07a252d77b3eba853890fcae
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1624087
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2017-12-26 15:15:39 -08:00
Seema Khowala
488d02944b gpu: nvgpu: gv11b: host1x probed only if syncpoints supported
Change-Id: I645f272f8fc3fffda95a82716558c081e323aed0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1624097
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
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2017-12-26 15:15:35 -08:00
Thomas Fleury
28a642f6bb gpu: nvgpu: vgpu: allow disabling of ctxsw tracing
Fixed build failure that occurred when disabling FECS ctxsw
tracing using CONFIG_GK20A_CTXSW_TRACE.

JIRA EVLR-2162

Change-Id: I751eba835c5f3f527571167e8b05fadb9687c64d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1617557
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Dennis Kou <dkou@nvidia.com>
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2017-12-14 14:28:09 -08:00
Terje Bergstrom
159d77a69d gpu: nvgpu: Require TSGs for CE always
All channels should be wrapped in TSGs so that bare channel support
can be dropped. Bind all CE channels to TSGs.

Bug 1842197

Change-Id: Ia55748d5b53750d860f7764b532ef9eeb6f214b8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1616693
2017-12-14 10:05:59 -08:00
Seema Khowala
1bf9b91c05 gpu: nvgpu: gv11b: get syncpt aperture only if host1x is present
nvgpu_get_nvhost_dev will not return error if host1x field within
gv11b device tree is not present. It will just set has_syncpoints
in gk20a struct to false. syncpt_unit_interface* should be called
only if g->has_syncpoints is set to true.

Change-Id: Id1eb94aba4cff1942ad519f528ebdb8291963971
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1615973
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2017-12-13 21:23:11 -08:00
Terje Bergstrom
b92a6bdbf5 gpu: nvgpu: Use TSG for CDE channels
All channels should be wrapped in TSGs so that bare channel support
can be dropped. Bind all CDE channels to TSGs.

Bug 1842197

Change-Id: I20b68c81b47e0d742e5922e7b85ac5cba75984b0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1616698
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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2017-12-13 17:21:35 -08:00
Terje Bergstrom
6e3f9112ea gpu: nvgpu: Disallow use of bare channels
All channels need to now be wrapped in TSGs. Disallow use of bare
channels by preventing creation of GPFIFO for them.

Bug 1842197

Change-Id: Id0ebee4c590804b96c09f8951e35ba2680b596e7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612697
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-12-12 14:03:57 -08:00
Richard Zhao
3cb9cd5267 gpu: nvgpu: vgpu: remove PMU setup in gv11b hal
vgpu doesn't care about pmu. pmu is managed by RM server.
It also fixed the dump caused by reading fuse register.

Jira EVLR-1934

Change-Id: I779964950783ccf699cd99473fb30e811c5c2ed6
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612774
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2017-12-11 16:42:08 -08:00
David Nieto
258ae44712 gpu: nvgpu: gv11b: PMU parity HWW ECC support
Adding support for ISR handling of ECC parity errors for PMU unit and setting
the initial IRQDST mask to deliver ECC interrupts to host in the non-stall
PMU irq path

JIRA: GPUT19X-83

Change-Id: I8efae6777811893ecce79d0e32ba81b62c27b1ef
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1611625
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2017-12-11 16:42:01 -08:00
Terje Bergstrom
ba69628aaf gpu: nvgpu: Use device_is_iommuable() only for iGPU
device_is_iommuable() is defined only in Tegra kernel. There is no
explicit config option to check for its existance, so skip building
that code when Tegra iGPU is not supported.

Change-Id: I50dc47070fa416181d458beabf5a2f2373931331
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612649
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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2017-12-11 08:31:40 -08:00