This patch adds SWUD (SW Unit Design) document for SDL unit. In addition,
it re-names err_type to err_id in error reporting APIs related to ECC, GR,
PRI and MMU, to keep the name consistent with other APIs.
JIRA NVGPU-3758
Change-Id: I968218574aa78144497fc12bd6dab20d1be7aa1c
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2151092
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Shortcomings of ALIGN macros:
- ALIGN_MASK down aligns when there is an wrapping/overflow instead of
throwing an error. This can affect the size assumptions.
- Alignment a's check will be bypassed when ALIGN_MASK is directly
used.
Fix these issues by 1) adding compile time error for non-unsigned type
arguments 2) using unsigned type safe ops for addition and subtraction.
Also, change users of ALIGN to pass unsigned types only.
JIRA NVGPU-3515
Jira NVGPU-3411
Change-Id: I5b94a262e09aad473c420af750ead6b0f9d36a9b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128382
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Safety build does not support vidmem. This patch compiles out vidmem
related changes - vidmem, dma alloc, cbc/acr/pmu alloc based on
vidmem and corresponding tests like pramin, page allocator &
gmmu_map_unmap_vidmem..
As vidmem is applicable only in case of DGPUs the code is compiled
out using CONFIG_NVGPU_DGPU.
JIRA NVGPU-3524
Change-Id: Ic623801112484ffc071195e828ab9f290f945d4d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132773
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- This patch replaces "nvgpu_current_time_ms" with "nvgpu_hr_timestamp_us".
- "nvgpu_hr_timestamp_us" gives timestamp in microseconds and has better
accuracy than "nvgpu_current_time_ms" (which gives timestamp in millisecond)
Bug 200503143
Change-Id: I6a10e8e1b3e8ff842aa23f58bf2ba9344af232a6
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
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INT30-C Requires that unsigned integer operations do not wrap.
INT31-C Requires that integer conversions do not result in lost or
misinterpreted data.
ERR33-C Requires to detect and handle standard library errors.
Fix the above CERT C violations in kmem unit.
Jira NVGPU-3603
Change-Id: I104551406e3cf6d2da22c5b6c6edc6694992ce62
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2139529
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Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset. OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.
Jira NVGPU-3545
Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129513
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Do not ignore volatile attribute of addr while assigning it to p.
Error: CERT EXP32-C:
drivers/gpu/nvgpu/os/posix/bitmap.c:227:
cert_violation: Access volatile variable "addr" through
a nonvolatile reference.
Jira NVGPU-3560
Change-Id: I202b143e1818641b12f6552810953ac447348271
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122720
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Make the nvgpu_init_mutex function return void.
In linux case, this doesn't affect anything since mutex_init
returns void.
For posix, we assert() and die if pthread_mutex_init fails.
This alleviates the need to error inject for _every_
nvgpu_mutex_init function in the driver.
Jira NVGPU-3476
Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130538
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Move all unit test specific code in bug unit under the define
__NVGPU_UNIT_TEST__. With this change the following MISRA violations
in bug unit will be only for UT specific code,
MISRA rule 11.3
MISRA rule 21.4
MISRA rule 21.5
Jira NVGPU-3294
Change-Id: I54d3fc2bb6f1f8bc319443c522cb7036d37368e6
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129285
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Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
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This patch does the following:
(1) Removes the usage of hw headers in SDL unit. For this purpose, it moves
the initialization required for errors that can be injected using hw
support, error injection function. Further, it passes the required
information to SDL via hal layers.
(2) Renames (i) PWR as PMU, (ii) nvgpu_report_ecc_parity_err to
nvgpu_report_ecc_err.
Jira NVGPU-3235
Change-Id: I69290af78c09fbb5b792058e7bc6cc8b6ba340c9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112837
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
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This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.
Jira NVGPU-3237
Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
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MISRA rule 21.1 states that #define and #undef shall not be used on
a reserved identifier or reserved macro name. Fix violations of
rule 21.1 in bitops unit.
MISRA rule 21.2 states that a reserved identifier or macro name
shall not be declared. Fix violations of rule 21.2 in bitops unit.
Jira NVGPU-3545
Change-Id: Ie551d7ce5e19287107403f2c991bcc55bd11a4e8
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125842
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MISRA rule 21.1 forbids the use of #define and #undef on a reserved
identifier or reserved macro name. Fix violations of rule 21.1 in
os_sched unit.
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore. Fix violation of MISRA rule 21.2 in os_sched unit.
Jira NVGPU-3299
Change-Id: Ib772f60adf5e81935f9cd2044ff8f6a402e15d82
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121955
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For some units, we want to use register spaces with
data already initialized with power-on register values.
Added the following routines:
- nvgpu_posix_io_register_reg_space
- nvgpu_posix_io_unregister_reg_space
Jira NVGPU-3476
Change-Id: Id4f5beb5e5d6b4af795e2eb58ccee13d2cfa6da5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120563
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MISRA Rule 11.2 doesn't allow conversion to or from an incomplete type
pointer, as it may result incorrect point alignment and may further lead
to undefined behavior.
MISRA Rule 16.x requires all switch statements to be well-formed with
terminating break statement for every switch-clause.
This patch fixes 11.2 and 16.x violations in common.mm.nvgpu_mem.
Jira NVGPU-3339
Change-Id: I002393cc64d44826e6954d1bf6af71bd569e862f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113096
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The LSB is position 1 for ffs and LSB is position 0 for __fls. Fix the
issue with the return values of ffs and __fls to follow the mentioned
bit positions.
Jira NVGPU-2149
Change-Id: I4deab420c62217f8ad90683397c38530f88467d2
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107276
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix the violations of MISRA rule 17.7 in posix lock unit.
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore. Fix the violations of MISRA rule 21.2 in posix lock
unit.
Jira NVGPU-3139
Change-Id: Ia7867071760708d4283cfa8430a2b95b81532356
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107237
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Make a hal/mm/gmmu sub-unit for the GMMU HAL code. Also move the
gk20a specific HAL code there. gp10b will happen in the next patch.
This change also updates all the GMMU related HAL usage, of which
there is quite a bit. Generally the only change is a .gmmu needs to
be inserted into the HAL path. Each HAL init was also updated.
JIRA NVGPU-2042
Change-Id: I6c46bdfddb8e021f56103d9457fb3e2a226f8947
Signed-off-by: Alex Waterman <alexw@nvidia.com>
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