This patch brings a number of changes to the mm.vm unit test:
- test_map_buf: add steps to check for error cases and increase
coverage.
- test_map_buf_gpu_va: add steps to check for error cases and
increase coverage.
- test_init_error_paths: new test to target all possible error
paths in the VM init code.
- test_map_buffer_error_cases: new test to target all possible
error paths in the buffer mapping logic.
- test_nvgpu_vm_alloc_va: new test to target the nvgpu_vm_alloc_va
API and also target error paths.
- test_vm_bind: new test to target the nvgpu_vm_bind_channel API
and also target error paths.
- test_vm_aspace_id: new test to target the vm_aspace_id API
and also target error paths.
JIRA NVGPU-909
Change-Id: I755c89a6de09376d2624130a98966c172d850bfe
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217679
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For some units that depend on libraries, tmake generates
what seems to be stub libraries, with all functions
implemented as a simple 'ret' instruction.
For instance, libfalcon_utf.so can be seen in multiple places:
du -b $(sudo find . -name libfalcon_utf.so)
7808 ./nvidia/kernel/nvgpu/userspace/units/pmu-l4t_64/libfalcon_utf.so
7808 ./nvidia/kernel/nvgpu/userspace/units/acr-l4t_64/libfalcon_utf.so
7808 ./nvidia/kernel/nvgpu/userspace/units/falcon/falcon_tests-l4t_64/libfalcon_utf.so
76968 ./nvidia/kernel/nvgpu/userspace/units/falcon-l4t_64/libfalcon_utf.so
76968 ./systemimage/home/nvgpu_unit/units/libfalcon_utf.so
The "real" library is in falcon-l4t_64/, and it contains actual code.
But install-unit.sh copies all *.so files to nvgpu_unit/units on target.
In some cases, we end up with a "stub" library being used instead of
the expected one.
To avoid this, make sure to copy the largest libraries (in bytes) last.
Also, remove the '-u' option of rsync to force the copy.
Jira NVGPU-4089
Change-Id: I3832373db9c5aa72ad9ce59eb09ec031609a69e4
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215319
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-Renamed ACR structs for FUSA, ACR FUSA code has struct names
ending with _v1 & ACR non-FUSA with _v0, removed _v1 for FUSA
code to keep struct without any versioning for doxygen.
-Renamed acr_blob_construct_v1.c/h to acr_blob_construct.c/h
JIRA NVGPU-2516
Change-Id: Id2d5e48e8169ce59371c2b08d04c5a65ba94c685
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2218265
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Add support for interrupt unit tests for following use cases
1. with channel and without tsg.
2. with channel and tsg, without setting the context to local cache.
3. with channel and tsg, setting the context to local cache
Jira NVGPU-4096
Change-Id: Ib9e5b49f5c5b94d785b9e225a84f3b2829fd3cf7
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213089
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IRQs can get triggered during nvgpu power-on due to MMU fault, invalid
PRIV ring or bus access etc. Handlers for those IRQs can't access the
full state related to the IRQ unless nvgpu is fully powered on.
In order to let the IRQ handlers know about the nvgpu power-on state
gk20a.power_on_state variable has to be protected through spinlock
to avoid the deadlock due to usage of earlier power_lock mutex.
Further the IRQs need to be disabled on local CPU while updating the
power state variable hence use spin_lock_irqsave and spin_unlock_-
irqrestore APIs for protecting the access.
JIRA NVGPU-1592
Change-Id: If5d1b5e2617ad90a68faa56ff47f62bb3f0b232b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203860
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Add unit tests for:
- gv11b_tsg_init_eng_method_buffers
- gv11b_tsg_deinit_eng_method_buffers
- gv11b_tsg_bind_channel_eng_method_buffers
- gv11b_tsg_unbind_channel_check_eng_faulted
Note: gv11b_tsg_enable was already tested as part of TSG common.
Added SWUTS documentation for above tests.
Modified gv11b_tsg_init_eng_method_buffers to inline computation
of method buffer size, as existing static function could never
return 0, making one branch not testable.
Added dummy IO register spaces for PFB, CE, PBUS and HSUB_COMMON,
so that g->ops.mm.init_mm_support can be called as part of
test_fifo_init_support. MM support is needed to test allocation
and mapping of DMA buffers.
Jira NVGPU-3788
Change-Id: I5356531b23c0456662187d16b35955bf0e528782
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207384
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Remove the second parameter for the pmu_early_init() and pmu_init()
functions so they only require the gk20a object. The g->pmu was always
passed for this parameter. And this makes the API signature match the
other init functions in the driver.
JIRA NVGPU-3980
Change-Id: Iae9361a5f14bc5c1d02f4ddb6583f30b71b22d59
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202968
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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This patch adds unit testing for the mm.as unit including:
- feature tests
- error injection testing
- 100% line coverage and 96% branches (one missing branch that
cannot be tested or removed)
JIRA NVGPU-917
Change-Id: I54bdac21e56554d1d960955f1a140ab98c9f3e5e
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194399
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Remove branch F_CHANNEL_SETUP_BIND_HAS_GPFIFO_MEM from the unit test
for nvgpu_channel_setup_bind as gpfifo_mem belongs to KMD and are not
part of safe builds.
Remove assignment of stub_userd_setup_sw as USERD is compiled out for
safe build.
Jira NVGPU-3172
Change-Id: I4ba72043cb97d8804887c2bed30af9d01dca563e
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2142941
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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The parallel unit testing is simply too buggy due to unit tests
not being completely independent. We need to determine exactly
what they are sharing and get rid of that.
For now, force unit tests to run one at a time. This should help
avoid many of the race conditions we see.
Bug 2711887
Change-Id: I04de51998b907d2c2195ea56f6092bbf76ffa1e3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204721
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Joshua Widen <jwiden@nvidia.com>
Tested-by: Joshua Widen <jwiden@nvidia.com>
Statically initialized nvgpu_posix_io_reg_space structures are
used in test_fifo_setup_gv11b_reg_space to initialize register spaces.
If fifo, TSG and channel unit tests run concurrently, the same
register space structure can be registered multiple times for
different GPU contexts. This results in list corruption or
use of freed memory.
Use allocated register spaces instead.
Jira NVGPU-3943
Change-Id: I74c080f336e32149d2a378e2b15d37a2bd60ff71
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204062
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
