Vedashree Vidwans
6f21c665ce
gpu: nvgpu: fix MISRA errors nvgpu.hal.fifo.ramin
...
Rule 8.6 requires each identifier with external linkage to have exactly
one external definitions.
This patch fixes rule 8.6 violations in nvgpu/hal/fifo/ramin_gk20a.h.
Jira NVGPU-3821
Change-Id: Ie3d6ddea330b9e504bd2157bd853b9db5fb8bfc4
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2154375
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com >
Reviewed-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-by: Adeel Raza <araza@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-07-22 11:55:18 -07:00
Thomas Fleury
4ef4939797
gpu: nvgpu: add base_shift and alloc_size ramin HALs
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Added the following HALs
- ramin.base_shift
- ramin.alloc_base
Use above HALs in mm, instead of using hw definitions.
Defined nvgpu_inst_block_ptr to
- get inst_block address,
- shift if by base_shift
- assert upper 32 bits are 0
- return lower 32 bits
Added missing #include for <nvgpu/mm.h>
Jira NVGPU-3015
Change-Id: I558a6f4c9fbc6873a5b71f1557ea9ad8eae2778f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2077840
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-04-07 15:54:10 -07:00
Thomas Fleury
04e156f09d
gpu: nvgpu: add set_adr_limit to ramin HAL
...
Added the following HAL
- ramin.set_adr_limit
Jira NVGPU-3015
Change-Id: I7982bbf46a2f26cfba3b4f5986b533f79b299038
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2077839
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-04-03 09:55:38 -07:00
Thomas Fleury
ba4bfe7fdf
gpu: nvgpu: move init_pdb to ramin HAL
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Replaced the following HAL
- mm.init_pdb
With
- ramin.init_pdb
Jira NVGPU-3015
Change-Id: Ie77aad5c5f83ef263b46739a52986296aca05468
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2077838
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-04-03 09:55:23 -07:00
Thomas Fleury
26a94593e5
gpu: nvgpu: add set_gr_ptr to ramin
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Added ramin unit under common/fifo
Added hal to set gr ctx (or subctx) in ramin:
- ramin.set_gr_ptr
Implemented
- gk20a_ramin_set_gr_ptr
- gv11b_ramin_set_gr_ptr
Jira NVGPU-3015
Change-Id: I79d7e7c9819ecf27e02ef44a89143c567df89af8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2075940
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-04-03 09:54:54 -07:00
