Commit Graph

22 Commits

Author SHA1 Message Date
David Ung
26de95b55f gpu: nvgpu: initialize masks for the perfmon counters 3
Initialize the perfmon counters #3 masks to be same values as ELPG.
Hardware boots up with value NV_PPWR_PMU_IDLE_MASK_1(3) (0x10aa4c) = 0x1030,
but ELPG NV_PPWR_PMU_IDLE_MASK_1_SUPP(0) (0x10a9f4) boots up with 0.

Bug 2833620

Change-Id: I026ab236fd42f4f9c61e2f9b1f2b7988711a2927
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335299
(cherry picked from commit bbef4c6927)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2422675
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2020-12-15 14:13:28 -06:00
mkumbar
918fa1a658 gpu: nvgpu: PMU NS ucode boot update
Removed gpmu_ucode.bin usage by fetching PMU ucode descriptor
and image from respective files for NS boot.

JIRA NVGPU-5183

Change-Id: I597c5dd17b4a58603f550b32980d7d0ca9624aed
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2376448
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2020-12-15 14:13:28 -06:00
Divya Singhatwaria
6b7527dd0e gpu: nvgpu: Add more branch coverage for PMU and ACR
Adding test scenarios to cover branches for
g->ops.pmu.pmu_isr
nvgpu_pmu_reset
nvgpu_acr_bootstrap_hs_acr
nvgpu_acr_init

Adding new test test_is_pmu_supported()

Also, moved gv11b_write_dmatrfbase() and the related ops
.write_dmatrfbase to non-fusa code under the flag
CONFIG_NVGPU_LS_PMU

JIRA NVGPU-2192
JIRA NVGPU-4319

Change-Id: I489ec5078756d68a4fdb37658e4a89b0d45f8963
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2283715
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Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2020-12-15 14:13:28 -06:00
Divya Singhatwaria
4b0499498b gpu: nvgpu: Unit tests for common.hal.pmu.pmu
Updating the test case to cover the
following ECC API:
- gv11b_pmu_ecc_init()

Also, since g->ops.pmu.secured_pmu_start is
called from nvgpu_pmu_rtos_init() (non-safe code)
so moved gv11b_secured_pmu_start() function under
CONFIG_NVGPU_LS_PMU flag

JIRA NVGPU-2192

Change-Id: Ia8d0386e81010b21b40437654c1f1667a450e060
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2274227
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2020-12-15 14:10:29 -06:00
Sagar Kamble
fba516ffae gpu: nvgpu: enable PMU ECC interrupt early
PMU IRQs were not enabled assuming entire functionality for LS PMU.
Debugging early init issues of PMU falcon ECC errors triggered
during nvgpu power-on will be cumbersome if interrupts are not
enabled early. FMEA analysis of the nvgpu init path also
requires this interrupt be enabled earlier.

Hence, Enable the PMU ECC IRQ early during nvgpu_finalize_poweron.
pmu_enable_irq is updated to enable interrupts differently for
safety and non-safety. PMU interrupts disabling is moved out
of nvgpu_pmu_destroy to nvgpu_prepare_poweroff. Prepared new
wrapper API nvgpu_pmu_enable_irq.

PMU ECC init and isr mutex init is moved to the beginning of
nvgpu_pmu_early_init as for safety, ls pmu code path is
disabled. Fixed the pmu_early_init dependent and mc
interrupt related unit tests.

Update the doxygen for changed functions.

JIRA NVGPU-4439

Change-Id: I1a1e792d2ad2cc7a926c8c1456d4d0d6d1f14d1a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2251732
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2020-12-15 14:10:29 -06:00
Sagar Kamble
ec293030c1 gpu: nvgpu: move non-safe functions from fusa hal to non-fusa hal
Multiple non-safe functions under NVGPU_DEBUGGER, NVGPU_CILP and other
config flags were moved to fusa files. Although they are guarded by
the C flags, it makes sense to keep those functions in non-fusa
files. Make this change for all hals.

JIRA NVGPU-3853

Change-Id: I8151b55a60cb50c5058af48bab9e8068f929ac3b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204352
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2020-12-15 14:05:52 -06:00
Sagar Kamble
ccef4f9c56 gpu: nvgpu: split pmu_gv11b fusa/non-fusa hal
gv11b_pmu_inject_ecc_error is needed in fusa functions. Hence moved it
to pmu_gv11b_fusa.c. Moved compilation of pmu_gv11b.c under NON_FUSA
and updated the arch.

JIRA NVGPU-3690

Change-Id: I88488591a72b8e43eccba44fc2afe4d0b5973a1c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156875
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2019-07-19 18:19:25 -07:00
Sagar Kamble
9bb347edec gpu: nvgpu: fix the hw header accessors
Various gv11b register accessors are passed as function pointer to
NVGPU_ECC_ERR. pmu logic needs access to head, tail, mutex registers
as function pointers. fix the same.

JIRA NVGPU-3733

Change-Id: I5668fedaac187fab052ee5d68a10f7e2d6d35413
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150880
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2019-07-12 06:20:44 -07:00
Debarshi Dutta
69ef86e627 gpu: nvgpu: move safe code HAL files to fusa
This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.

Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.

Jira NVGPU-3690

Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
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Reviewed-by: Sagar Kamble <skamble@nvidia.com>
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2019-07-03 02:46:15 -07:00
Sagar Kamble
3f08cf8a48 gpu: nvgpu: rename feature Make and C flags
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>

s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG

JIRA NVGPU-3624

Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130290
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2019-06-11 09:46:24 -07:00
Mahantesh Kumbar
b691df5a02 gpu: nvgpu: compile out PMU members & headers for safety
-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files

JIRA NVGPU-3418

Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
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2019-06-06 06:55:58 -07:00
Rajesh Devaraj
05ed37ae3a gpu: nvgpu: remove usage of hw headers from SDL
This patch does the following:
(1) Removes the usage of hw headers in SDL unit. For this purpose, it moves
    the initialization required for errors that can be injected using hw
    support, error injection function. Further, it passes the required
    information to SDL via hal layers.
(2) Renames (i) PWR as PMU, (ii) nvgpu_report_ecc_parity_err to
    nvgpu_report_ecc_err.

Jira NVGPU-3235

Change-Id: I69290af78c09fbb5b792058e7bc6cc8b6ba340c9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112837
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
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2019-05-31 04:06:51 -07:00
Mahantesh Kumbar
90aee0086f gpu: nvgpu: rename NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU
renamed NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU to follow
nvgpu naming standard
Compile out LS PMU files when PMU RTOS support is
disabled for safety build by setting NVGPU_LS_PMU
build flag to 0

JIRA NVGPU-3418

Change-Id: Ib09924ac25657e932723c10be573f2f701cb7bea
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127794
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2019-05-30 19:27:14 -07:00
Mahantesh Kumbar
e10e0bee08 gpu: nvgpu: compile out LS PMU HAL code for safety
Compile out PMU RTOS specific PMU HAL code when
PMU RTOS support is disabled for safety build by setting
NVGPU_LS_PMU build flag to 0

Added new functions for gv11b PMU HAL to easy compile out
other PMU HAL files.

Replaced all gk20a_writel/readl calls with nvgpu_writel/readl
calls in hal/pmu/pmu_gv11b.c files

JIRA NVGPU-3418

Change-Id: I7c315349aa95721990dc7b1570383669bcb6221f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117691
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2019-05-30 19:25:08 -07:00
Rajesh Devaraj
fcb7635a92 gpu: nvgpu: gops initialization for SDL
This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
  reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.

Jira NVGPU-3237

Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
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2019-05-30 02:18:05 -07:00
Antony Clince Alex
ce3c2a3c43 gpu: nvgpu: validate PMU I/DMEM integrity at end of HS bootstrap
The HS ucode runs on PMU with all interrupts disabled. So it will not be
able to detect any data corruption introduced in the IMEM or DMEM due to bit
flips. In order to mitigate this issue validate the integrity of IMEM and DMEM
at the end of HS ucode bootstrap and fail the boot incase of any un-corrected
errors.

Jira NVGPU-3555

Change-Id: Icd9a2bf2c29470629be8524c9b99f90e3036abdc
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124107
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2019-05-26 22:37:31 -07:00
Mahantesh Kumbar
3d1169544f gpu: nvgpu: alloc space for PMU's struct nvgpu_pmu at runtime
Allocating space for struct nvgpu_pmu at run time as part of
nvgpu_pmu_early_init() stage and made required changes to
dependent fiels as needed.

JIRA NVGPU-1972

Change-Id: I2d1c86d713e533c256ba95b730aa2e9543a66438
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110109
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2019-05-23 00:56:55 -07:00
Mahantesh Kumbar
25364895fd gpu: nvgpu: PMU RTOS fw init update
Allocate space at runtime for PMU RTOS fw struct, this helps
to reduce the size of nvgpu_pmu struct when LS_PMU support
is not required.

Allocation happens at pmu early init stage & will deinit at
remove_support stage.

JIRA NVGPU-1972

Change-Id: I1452b085f8d3a76e12186f788c2d999a8b4b202d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111072
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2019-05-14 04:56:34 -07:00
Sagar Kamble
538a471c97 gpu: nvgpu: address CCM deviations for gv11b_pmu_handle_ext_irq
gv11b_pmu_handle_ext_irq CCM value was higher than 10. Address by
separating ecc handling to new function gv11b_pmu_handle_ecc_irq
and gv11b_pmu_correct_ecc. Also address checkpatch issues.

JIRA NVGPU-3194

Change-Id: I3549c79227508a36635225ff4c19b1f8388b4a1f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101946
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2019-04-26 14:18:46 -07:00
Mahantesh Kumbar
9108ae3c62 gpu: nvgpu: create PMU FW unit
Created PMU fw unit to hold PMU RTOS f/w specific ops, images,
flags & command arguments needed for PMU RTOS ucode support.

Moved PMU fw ops from gk20a.gpu_ops to pmu.fw.ops as these ops
are needed to support different version of PMU fw version for
different chips

JIRA NVGPU-1955

Change-Id: I51385d8c20524431f07cba3378676464663deb20
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090769
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2019-04-24 02:34:20 -07:00
Mahantesh Kumbar
05f27e8b64 gpu: nvgpu: PMU HAL non-secure bootstrap clean up
Moved/cleaned non-secure PMU bootstrap code from PMU HAL
to common/pmu to remove PMU HAL dependency on pmu interfaces

JIRA NVGPU-2002

Change-Id: Ie47e12833c79a8a93eb01dfd37d867ed7596e5c0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094837
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2019-04-24 02:34:05 -07:00
Mahantesh Kumbar
2cf8feedd8 gpu: nvgpu: Create PMU HAL
Moved PMU HAL code from common/pmu/pmu_chip.c/h to hal at path
hal/pmu/pmu_chip.c/h file.

some code may need more cleanup but will take care in new patches

JIRA NVGPU-2002

Change-Id: I281a2c15e55292e0716b0a4c71f4469c97dd71ab
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089410
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2019-04-16 02:54:46 -07:00