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ef1fb41e54893e37f649877b2b19fea705e7c08c
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11 Commits

Author SHA1 Message Date
Divya
ef1fb41e54 gpu: nvgpu: add pmu hals to resolve mismatch 
Add the following HALs to avoid the duplication
of code for future chips:
- set_mailbox1
- get_ecc_address
- get_ecc_status
- set_ecc_status

JIRA NVGPU-9758

Change-Id: I54ce3dfaae2873dbcd88edabbd877eca9f3d1fdb
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2898016
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-16 06:27:08 -07:00
Divya
a4175b1265 gpu: nvgpu: resolve pmu mismatches 
Add the following pmu HALs for PMU registers
to avoid duplication of code for future chips:
- get_bar0_addr
- get_bar0_data
- get_bar0_timeout
- get_bar0_ctl
- get_bar0_error_status
- set_bar0_error_status
- get_bar0_fecs_error
- set_bar0_fecs_error
- get_mailbox
- get_pmu_debug

JIRA NVGPU-9758

Change-Id: If8b9c91ecd51d526babf12e3cee09048d736f0f4
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2897156
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-05 19:48:04 -07:00
Divya
b54cb9fd97 gpu: nvgpu: add pmu hals 
Add the following HALs for following PMU registers:
- get_irqstat
- set_irqsclr
- set_irqsset
- get_exterrstat
- set_exterrstat
- get_exterraddr

JIRA NVGPU-9758

Change-Id: Ib153d3189ff493fdb726ec2d1e81b863476fc667
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2886108
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-04-21 11:33:56 -07:00
mkumbar
c62cfa2efb gpu: nvgpu: get PMU NEXT core irqmask 
-Add new PMU ops to get NEXT core irq mask
-Add support to handle NEXT core interrupt request.

Bug 200659053
Bug 3199589

Change-Id: I78738f074a425f8934bbba28bf6996eeec7ab05a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457077
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
Joshua Widen
60f44506a3 Revert "gpu: nvgpu: get PMU NEXT core irqmask" 
This reverts commit 4ff427c51619cecdcc74fdbb388d82421cf45655.

Reason for revert: Testing for regression seen in GVS.

Bug 3198736

Change-Id: If12da341c3e13907bdcbb778c8fb4118cd5e3803
Signed-off-by: jwiden <jwiden@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2456791
Reviewed-by: svcguardwords <svcguardwords@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
mkumbar
8284832300 gpu: nvgpu: get PMU NEXT core irqmask 
-Add new PMU ops to get NEXT core irq mask
-Add support to handle NEXT core interrupt request.

Bug 200659053

Change-Id: I8b1c9b9d74ed59b4130fea712f970b4a31a8b4fe
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2429042
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
Sagar Kamble
fba516ffae gpu: nvgpu: enable PMU ECC interrupt early 
PMU IRQs were not enabled assuming entire functionality for LS PMU.
Debugging early init issues of PMU falcon ECC errors triggered
during nvgpu power-on will be cumbersome if interrupts are not
enabled early. FMEA analysis of the nvgpu init path also
requires this interrupt be enabled earlier.

Hence, Enable the PMU ECC IRQ early during nvgpu_finalize_poweron.
pmu_enable_irq is updated to enable interrupts differently for
safety and non-safety. PMU interrupts disabling is moved out
of nvgpu_pmu_destroy to nvgpu_prepare_poweroff. Prepared new
wrapper API nvgpu_pmu_enable_irq.

PMU ECC init and isr mutex init is moved to the beginning of
nvgpu_pmu_early_init as for safety, ls pmu code path is
disabled. Fixed the pmu_early_init dependent and mc
interrupt related unit tests.

Update the doxygen for changed functions.

JIRA NVGPU-4439

Change-Id: I1a1e792d2ad2cc7a926c8c1456d4d0d6d1f14d1a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2251732
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Mahantesh Kumbar
525ff83910 gpu: nvgpu: Cleanup PMU unit header file pmu.h 
Moved PMU subunits specific defines from pmu.h to
respective subunits header file by renaming properly
as needed

JIRA NVGPU-2457

Change-Id: Id29a2d5cb028fc69049738c735c5585b6276b115
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199547
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Divya Singhatwaria
8948c91719 gpu: nvgpu: Fix MISRA violations in PMU unit 
- Rule 17.7 states that the value returned by a
  function having non-void return type shall be
  used.
- Add NVGPU_FEATURE_LS_PMU to compile out headers
  in pmu_gv11b.h to fix MISRA violation 8.6

JIRA NVGPU-3570

Change-Id: I6ab104aa72d8fd6419bd336c45e9055a40ba5a7e
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131420
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-14 09:06:06 -07:00
Mahantesh Kumbar
05f27e8b64 gpu: nvgpu: PMU HAL non-secure bootstrap clean up 
Moved/cleaned non-secure PMU bootstrap code from PMU HAL
to common/pmu to remove PMU HAL dependency on pmu interfaces

JIRA NVGPU-2002

Change-Id: Ie47e12833c79a8a93eb01dfd37d867ed7596e5c0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094837
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-24 02:34:05 -07:00
Mahantesh Kumbar
2cf8feedd8 gpu: nvgpu: Create PMU HAL 
Moved PMU HAL code from common/pmu/pmu_chip.c/h to hal at path
hal/pmu/pmu_chip.c/h file.

some code may need more cleanup but will take care in new patches

JIRA NVGPU-2002

Change-Id: I281a2c15e55292e0716b0a4c71f4469c97dd71ab
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089410
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-16 02:54:46 -07:00