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a4175b1265
Add the following pmu HALs for PMU registers to avoid duplication of code for future chips: - get_bar0_addr - get_bar0_data - get_bar0_timeout - get_bar0_ctl - get_bar0_error_status - set_bar0_error_status - get_bar0_fecs_error - set_bar0_fecs_error - get_mailbox - get_pmu_debug JIRA NVGPU-9758 Change-Id: If8b9c91ecd51d526babf12e3cee09048d736f0f4 Signed-off-by: Divya <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2897156 Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
90 lines
3.9 KiB
C
90 lines
3.9 KiB
C
/*
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* Copyright (c) 2011-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef PMU_GK20A_H
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#define PMU_GK20A_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_pmu;
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struct pmu_mutexes;
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#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6U
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#define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEADU
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void gk20a_pmu_isr(struct gk20a *g);
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u32 gk20a_pmu_get_irqmask(struct gk20a *g);
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u32 gk20a_pmu_get_irqstat(struct gk20a *g);
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void gk20a_pmu_set_irqsclr(struct gk20a *g, u32 intr);
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void gk20a_pmu_set_irqsset(struct gk20a *g, u32 intr);
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u32 gk20a_pmu_get_exterrstat(struct gk20a *g);
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void gk20a_pmu_set_exterrstat(struct gk20a *g, u32 intr);
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u32 gk20a_pmu_get_exterraddr(struct gk20a *g);
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u32 gk20a_pmu_get_bar0_addr(struct gk20a *g);
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u32 gk20a_pmu_get_bar0_data(struct gk20a *g);
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u32 gk20a_pmu_get_bar0_timeout(struct gk20a *g);
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u32 gk20a_pmu_get_bar0_ctl(struct gk20a *g);
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u32 gk20a_pmu_get_bar0_error_status(struct gk20a *g);
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void gk20a_pmu_set_bar0_error_status(struct gk20a *g, u32 val);
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u32 gk20a_pmu_get_bar0_fecs_error(struct gk20a *g);
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void gk20a_pmu_set_bar0_fecs_error(struct gk20a *g, u32 val);
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u32 gk20a_pmu_get_mailbox(struct gk20a *g, u32 i);
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u32 gk20a_pmu_get_pmu_debug(struct gk20a *g, u32 i);
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#ifdef CONFIG_NVGPU_LS_PMU
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void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);
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void gk20a_pmu_init_perfmon_counter(struct gk20a *g);
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void gk20a_pmu_pg_idle_counter_config(struct gk20a *g, u32 pg_engine_id);
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u32 gk20a_pmu_read_idle_counter(struct gk20a *g, u32 counter_id);
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void gk20a_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id);
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u32 gk20a_pmu_read_idle_intr_status(struct gk20a *g);
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void gk20a_pmu_clear_idle_intr_status(struct gk20a *g);
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void gk20a_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu);
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u32 gk20a_pmu_mutex_owner(struct gk20a *g, struct pmu_mutexes *mutexes,
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u32 id);
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int gk20a_pmu_mutex_acquire(struct gk20a *g, struct pmu_mutexes *mutexes,
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u32 id, u32 *token);
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void gk20a_pmu_mutex_release(struct gk20a *g, struct pmu_mutexes *mutexes,
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u32 id, u32 *token);
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int gk20a_pmu_queue_head(struct gk20a *g, u32 queue_id, u32 queue_index,
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u32 *head, bool set);
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int gk20a_pmu_queue_tail(struct gk20a *g, u32 queue_id, u32 queue_index,
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u32 *tail, bool set);
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void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set);
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u32 gk20a_pmu_get_irqdest(struct gk20a *g);
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void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable);
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void gk20a_pmu_handle_interrupts(struct gk20a *g, u32 intr);
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bool gk20a_pmu_is_interrupted(struct nvgpu_pmu *pmu);
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int gk20a_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status,
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u32 *etype);
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int gk20a_pmu_ns_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
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u32 args_offset);
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bool gk20a_pmu_is_engine_in_reset(struct gk20a *g);
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void gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset);
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void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr);
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u32 gk20a_pmu_falcon_base_addr(void);
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bool gk20a_is_pmu_supported(struct gk20a *g);
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#endif
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#endif /* PMU_GK20A_H */
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