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a4175b1265
Add the following pmu HALs for PMU registers to avoid duplication of code for future chips: - get_bar0_addr - get_bar0_data - get_bar0_timeout - get_bar0_ctl - get_bar0_error_status - set_bar0_error_status - get_bar0_fecs_error - set_bar0_fecs_error - get_mailbox - get_pmu_debug JIRA NVGPU-9758 Change-Id: If8b9c91ecd51d526babf12e3cee09048d736f0f4 Signed-off-by: Divya <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2897156 Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>