On host copy engine PBDMA interrupt, channel is aborted as part of the
recovery and its syncpt value is set to the max threshold.
Syncpoint may then get incremented by PBDMA (incr cmd gets processed)
after this interrupt is handled leading to syncpoint value becoming
greater than the max threshold.
Again while unbinding the channel, syncpoint value is incremented until
it reaches max threshold. Since syncpoint value is already greater than
max threshold, host1x version of nvgpu_nvhost_syncpt_set_minval will
loop for entire u32 range until it reaches max threshold and this
will hang the channel unbind.
nvgpu_nvhost_syncpt_set_minval can ensure the syncpoint value is greater
than or equal to max threshold. Hence update the check for syncpoint
value from not equal to less than.
Bug 3681100
Change-Id: I96e7a1f53d4037e9ed858a2e90dd5a8d17ed6bb0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2742604
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Enable/disable LSPMU interrupt in MC, as required LSPMU
interrupts are configured as part of LSPMU ucode init and
don't need any additional PMU IRQ register to set/clear as
part of GPU power-on/off sequence.
Bug 3681561
Change-Id: Ifb47bc9cc83e16e46649b0eef5f257acb02f302c
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2740623
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Add error reporting support for T194's L1SS safety
services for linux.
Used GA10B's LUT for GV11B. The error ids for T194 are
different compared to GA10B. This is handled by creating
a separate table mapping existing error ids to match GV11B.
Ids that are not used by GV11B are set to U32_MAX to indicate
the driver to not send them to the l1ss driver.
Bug 200588528
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: I10a267942df77458c3deee0aad1179955490aa74
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2736772
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
bpmp will floorsweep GPCs as per parameters to tpc_pg_mask sysfs.
While doing that corresponding GPC clocks are also disabled.
nvgpu should re-initialize the clocks every time the
GPC/TPC pg_masks are passed to bpmp mrq.
Also print error when clk_prepare_enable fails.
Introduce platform->clks_lock to protect access to platform->clks
and platform->num_clks done from unrailgate/railgate and bpmp
mrq set calls from sysfs.
Acquire static_pg_lock in railgate path to synchronize railgate
with sysfs.
Bug 3688506
Change-Id: I3203d78b87289e7a847d78b3117e2d3119be3425
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2738920
Reviewed-by: Amulya Yarlagadda <ayarlagadda@nvidia.com>
GVS: Gerrit_Virtual_Submit
To build nvgpu as external module NV_BUILD_KERNEL_OPTIONS dependency is
present to set the config CONFIG_NVGPU_NVMAP_NEXT.
Remove that dependency as rel-35 does not support kernels prior
to v5.10.
And nvlink symbols are not found while building with public sources.
nvlink is not supported on rel-35, hence disable that config.
Bug 3700823
Bug 3684625
Change-Id: I8787ecb9746dd010a025e6d53679d2f23578ad56
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2738479
Tested-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
When destroying a virtual memory pool the associated page size must
be set in the nvgpu_vm_remap_op structure.
This patch adds a new nvgpu_vm_remap_page_size_flag() routine that
converts the page size derived from the vm/vm_area structs to the
corresponding NVGPU_VM_REMAP_OP_FLAGS_PAGESIZE bit.
Bug 3669908
Change-Id: Idca77cc36d353777b399c872f68a1f5231ddb8dd
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2734822
Tested-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Enable DEVFREQ for OOT module unconditionally as the podgov governor
module.
linux/pm_qos is only used for downstream supported modifications
which is currently determined by CONFIG_GK20A_PM_QOS.
struct devfreq_dev_status doesn't have any field 'busy' in the upstream
driver hence enable it only for when downstream driver is in use
activated by CONFIG_GK20A_PM_QOS.
governor.h is only needed for android platforms which depend on 4.9
version of the kernel in downstream builds. Hence, added an compile
time flag to remove it for kernels versions greater than 4.9.
Jira LS-418
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: Id242bd28e66ed187208f0d7975ee0bc508730a88
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2705766
(cherry picked from commit e81d0e8ff8)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2734112
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
In the current setting, clock arbiter skips setting
the clock if its already set previously. The value
set by the arbiter is stored in
"struct nvgpu_clk_arb->actual" whenever the clock is
updated via the arbiter. However, DVFS might also
update the clock and the updates are not synchronized
with the arbiter. Hence, ensure that any clock
requests are always updated i.e. the requested rate is
set even if the previous rate remains the same.
Bug 3666615
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: I32bf4dbf81b19fdd6fa0bdec3a6c9a9312b78eca
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2732364
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
To be able to access the full physical memory range, gpu's dma_mask
needs to be set to the max value of H/W compatible range.
For example. In order to support from 2GB to 66 GB, GV11B's dma_mask
needs to be atleast 37 bits. Set GV11B's dma_mask to 38 bit
and T23X's dma_mask to 39 bit. These values are supported by H/W.
Bug 3656729
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: Icfff3c36a8c9cf074a254fa773c42e18020ae5de
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2723640
(cherry picked from commit 1bf9309f17)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2724566
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Brad Griffis <bgriffis@nvidia.com>
nvgpu_device_get can return NULL if supplied invalid ID or instance
ID. We expect GR device struct to be non-NULL there hence just
assert that it is indeed non-NULL in gr_reset_engine and
ga10b_grmgr_init_gr_manager.
CID 224133
CID 250232
Bug 3512546
Change-Id: Id09a1c436a8e49b921111b940d3d013bd66bff7a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2707018
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
As per Safety_Services, a client must perform polling to ensure that the
previously reported errors are cleared at FSI, in case of back-to-back
error reporting. However, to minimize the polling overhead, NvGPU driver
performs polling only when the error to be reported is corrected error
to ensure that it is not overwriting the previously reported
uncorrected/corrected error. In case of uncorrected errors, it will be
reported without doing polling. This situation leads to a failure in
error reporting, when uncorrected errors are reported back-to-back. This
is acceptable for safety builds where SW quiesce will be triggered
immediately after the reporting of first uncorrected error. In case of
other build configurations, MCU/SEH takes the decision on encountering
uncorrected errors. To handle such build configurations, polling is
enabled for all types of errors, in all build configurations.
This patch also removes an unused macro "ERR_TYPE_MASK".
Bug 3622420
Change-Id: I750b0406faec9b229d8d0c74e986807234362cb9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2707105
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit
There shouldn't be an usecase that an fd, installed by nvgpu,
must be shared on exec with the new process. This doesn't only
lead to excessive number of fds in the exec process, but also
can lead to potential security issues.
This patch marks the fds with O_CLOEXEC, so that they get
closed on exec.
Bug 3583628
Change-Id: I3499b1429ac512b2c172e9e628d0a7a1417d72e3
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2704350
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
The emulate mode support is determined after chip detect and is flagged
by using NVGPU_SUPPORT_EMULATE_MODE flag. The present logic prevents
user from configuring the emulate mode sysfs knobs if this flag is not
set, however the emulate mode usecase requires the user to configure the
syfs knob prior to power-on, hence defer emulate mode check to a later
stage after chip detect.
Bug 3621460
Change-Id: If522527542fa8d7e95ccbcff43b74adbb9e976e6
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2703953
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mayur Poojary <mpoojary@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: David Li <davli@nvidia.com>
Fix following Coverity defect:
cde.c : Unintentional integer overflow
The Coverity issue suggests that (u64) (nvgpu_ltc_get_ltc_count(g) * nvgpu_ltc_get_slices_per_ltc(g) * nvgpu_ltc_get_cacheline_size(g)) can cause overflow because typecasting is done after multiplication.
This patch solves that issue by typecasting it before multiplication.
CID 10112360
Bug 3460991
Signed-off-by: Jinesh Parakh <jparakh@nvidia.com>
Change-Id: I314ca7a9adc95fcb09f15eb603b56ad03ce34b99
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2697027
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Fixed following Coverity Defects:
ioctl_as.c : Bad bit shift operation
mc_tu104.c : Bad bit shift operation
vm.c : Bad bit shift operation
vm_remap.c : Bad bit shift operation
A new linux header file for ilog2 is created.
The files which used the old ilog2 function
have been changed to use the new nvgpu_ilog2
function.
CID 9847922
CID 9869507
CID 9859508
CID 10112314
CID 10127813
CID 10127899
CID 10128004
Signed-off-by: Jinesh Parakh <jparakh@nvidia.com>
Change-Id: Ia201eea7cc426c3d6581e1e5ae3b882dbab3b490
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2700994
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Fix following Coverity Defect:
nvgpu_init.c : Unused value
The ret variable was being reassigned the error code from
nvgpu_cic_mon_deinit(g) without taking into account the previous ret value.
We need to propagate whether there is an error
(the last known error is returned) or not using ret, the temp_ret
variable helps in verifying this.
Similar coding style followed in the entire function.
CID 10127863
Bug 3460991
Signed-off-by: Jinesh Parakh <jparakh@nvidia.com>
Change-Id: I732ba5269ebbbe68f113e53229df40ae49ccc13c
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2697104
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
The function nvgpu_profiler_unbind_pm_resources is responsible for
destroying the regops allowlist object, but unfortunately does it
prior to any of the failure-prone operations. Because this function
can be called multiple times, in rare cases it can happen that
object is deallocated twice.
This patch fixes the issue by moving the free operations after the
failure-prone operations.
Bug 3591603
Change-Id: I3415712da561ccf162c9fb7f3ebb942faa9d9420
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2693803
(cherry picked from commit I3415712da561ccf162c9fb7f3ebb942faa9d9420)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2693799
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Prior to starting any profiling session, GPU power features should be
disabled, not doing this can result in unexpected behavior, print a
error message under such situations.
Jira NVGPU-7326
Bug 3579926
Change-Id: Ia9716d73ed945a588792a7d843aed64bf3b7f83b
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2701501
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit
After the board boots up, we have a specific set of settings for
each power mode which contains, fbp, tpc mask values, cpu, gpu
frequencies etc. So, we need to make sure to provide all the setting
values for each mode so that those will be applied correctly.
So, the fbp, tpc, gpc mask could be same in different power modes
and since the golden image context check which comes before is
returning -ENODEV, the nvpmodel service fails to set the power mode.
Thus, we need to compare whether the fbp and gpc mask values are same
before we check for the golden image context.
Bug 3581634
Change-Id: I3fb1398d47cd37bf49ad70cf80b057d4b80dec04
Signed-off-by: Ninad Malwade <nmalwade@nvidia.com>
(cherry picked from commit a27e202402)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2688116
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
RO buffers should not be accessed via any paths in userspace/kernel.
vmap is one such path. nvmap now returns error if vmap is attempted
on RO buffer. However that leads to kernel warning. nvgpu should
ensure that buffer is RW before performing vmap on the buffer.
With this check, dma_buf_vmap will not be called for RO buffers.
Bug 3562426
Change-Id: I4782d2ae6b17243fdb3d0fc5d5d732a17f694a7c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2693976
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-by: Martin Radev <mradev@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Fix CERT issue in nvgpu_gr_falcon_bind_fecs_elpg where nvgpu_pmu_pg_buf
could return NULL. nvgpu_pmu_pg_buf is called from context where PG
will be enabled hence remove the NULL return logic as it is dead
code.
Replace nvgpu_pmu_pg_buf and nvgpu_pmu_pg_buf_get_cpu_va functions by
new function nvgpu_pmu_pg_buf_alloc.
CID 17860
Bug 3512546
Change-Id: I09820a966dadeb258167ce1433ca256f94845896
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2692466
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
In gk20a_ctrl_dev_ioctl clk_set_info: An unscrutinized value num_entries
is used as a loop bound. An attacker could control the number of times
the loop iterates.
Loop iterator is signed int which can lead to unpredictable results,
Hence change it to u32. And sanitize the num_entries parameter.
CID 1993996
Bug 3460991
Change-Id: Ib644cf19f016ab80a3f2d66f156ca863f8e138e1
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2693942
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Disable below interrupts on safety as they do not report any error
condition and are not used by CUDA and Graphics(VKSC) on safety
build.
Signoff from CUDA and VKSC is on Bug https://nvbugs/3588603
1. NV_PGRAPH_INTR_NOTIFY: This intr is set when the Notification
style is WRITE_THEN_AWAKEN.
2. NV_PGRAPH_INTR_SEMAPHORE: This is set when a 3d class sempahore is
released as the result ofa SetSemaphoreD method, when the
AwakenEnable field is TRUE.
3. NV_PGRAPH_INTR_BUFFER_NOTIFY: This bit is set when a Mem2mem DMA
completes and the LaunchDma method specifies the interrupt type
as INTERRUPT
4. NV_PGRAPH_INTR_DEBUG_METHODS: This is debug feature and not used
on QNX safety
Bug 3588603
JIRA NVGPU-8166
Change-Id: I6d07dfd2857ac047fac4599421600d364251df76
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2694363
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Update PES, ROP exception handling for NVGPU_ERRATA_3524791. Enable the
errata for all Volta+ chips.
ROP, PES exceptions are being reported using the physical-id,
where logical-id should have been used. All ESR status registers are
reported using logical-id, so this matches with the SW expectation.
To address the (1), update ROP, PES exception handler translate from
physical to logical-id before reading the status registers.
Bug 3524791
Change-Id: Ieacbfb306bb0e69cf0113dc92f18e401573722e3
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2680029
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Volta+ chips supports PES floorsweeping and Ampere+(iGPU) chips supports
ROP floorsweeping. At present, the driver isn't aware of PES, ROP
floorsweeping, make the driver PES, ROP floorsweeping aware by introducing the
following fields in nvgpu_gr_config:
- gpc_(rop/pes)_mask: Contains the bit mask of non FSed ROP/PES units per GPC.
- gpc_(rop/pes)_logical_id_map: Translates per GPC ROP/PES physical id to
logical id.
Introduce the following HAL functions to read PES/ROP FS data:
- gops_fuse.fuse_status_opt_(pes/rop)_gpc: This fuction gets the FS
config from the fuse.
- gops_top.get_max_(pes/rop)_per_gpc: Gets the maximum number of PES/ROP
units that can be present in a GPC.
In addition, introduce the enabled flag NVGPU_SUPPORT_PES_FS to identify chips
which support PES floorsweeping, piggyback on NVGPU_SUPPORT_ROP_IN_GPC
enabled flag to identify ROP floorsweeping.
Bug 3524791
Change-Id: I065bab6c02618fe38892c8c890b069c340b85301
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2679570
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Upstream commit 7938f4218168 ("dma-buf-map: Rename to iosys-map")
renames 'struct dma_buf_map' to 'struct iosys_map' and breaks building
the NVGPU driver with Linux v5.18-rc1. In the NVGPU driver there are
many places where 'dma_buf_map' is used and so to clean-up the code and
minimise the impact of this change, add a gk20a_dmabuf_vmap() and a
gk20a_dmabuf_vunmap() helper function. These new functions support all
kernel versions and eliminate a lot the KERNEL_VERSION ifdefs.
Bug 3598986
Change-Id: Id0f904ec0662f20f3d699b74efd9542d12344228
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2693970
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add new profiler resource type NVGPU_PROFILER_PM_RESOURCE_TYPE_PC_SAMPLER.
Introduce regops HAL get_hwpm_pc_sampler_register_ranges to get
allowlist for PC_SAMPLER resources. Re-generate allowlist files to include
register ranges for PC_SAMPLER resources.
Update uapi header to advertise new resource type
NVGPU_PROFILER_PM_RESOURCE_ARG_PC_SAMPLER.
Bug 3408536
Change-Id: I7009ef822665771eed727da48ef1e89dcc6b9c4b
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2689057
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
