Commit Graph

1387 Commits

Author SHA1 Message Date
Srikar Srimath Tirumala
fef62b02ab gpu: nvgpu: add missing header
Allow NA_GPCPLL to be enabled on T210 K4.4

Bug 200233943

Change-Id: I5ea0b9d1de51b510f5c6671339dee2953bf1ec80
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: http://git-master/r/1280829
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-30 16:34:24 -08:00
Srikar Srimath Tirumala
702ed11f94 Revert "gpu: nvgpu: fix gpcclk for K4.4"
This reverts commit a918003694.

Change-Id: Idf39cc0946c5c4df82c7c4b6afa225b1f8d5a923
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: http://git-master/r/1280827
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-30 16:34:12 -08:00
Terje Bergstrom
cf8d9ccf8e gpu: nvgpu: Base channel watchdog on gp_get
Instead of checking if a job is complete, only check that channel is
making progress by checking its gp_get is advancing.

This will make the watchdog conservative. Previously a whole job had
x seconds to complete. Now channel has x seconds to get host to
consume each push buffer segment.

Bug 1861838
Bug 200273419
Bug 200263100

Change-Id: I70adc1f50301bce8db7dac675771c251c0f11b70
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1294850
Reviewed-by: Automatic_Commit_Validation_User
2017-01-30 09:53:43 -08:00
Konsta Holtta
ed22056779 gpu: nvgpu: add disable_syncpoints debugfs node
To test semaphore-related bugs with igpus, add a debugfs node called
"disable_syncpoints" to override the "has_syncpoints" platform flag.
This makes job synchronization use semaphores, for example.

NVGPU_GPU_FLAGS_HAS_SYNCPOINTS is still reported in gpu characteristics
if the platform supports that, because it is filled in during boot.

Jira NVGPU-18

Change-Id: I58c815f896a6054df472f571012c239f1478bf07
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1293972
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-27 13:54:41 -08:00
seshendra Gadagottu
88ce7a98c8 gpu: nvgpu: update zcull and pm context pointers
Update zcull and perfmon buffer pointers in context
header through function pointers.

JIRA GV11B-48

Change-Id: Iaa6dd065128cb0c39e308cecf17b9d68a826d865
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1291850
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-27 12:23:01 -08:00
Terje Bergstrom
fa3f8cc101 gpu: nvgpu: Remove circular dependency in PMU includes
Remove including gk20a.h from pmu_gk20a.h. This causes a fallout
as some #includes were missing.

gr_gp10b.h uses mem_desc, but did not include mm_gk20a.h. Add the
include.

Including mm_gk20a.h in gr_gp10b.h causes recursive include, as
mm_gk20a.h has some gr defines. Move the defines to gr_gk20a.h to
remove the dependency.

gr_ctx_gk20a.h used struct gk20a pointers, but did not forward
declare it. Add a forward declaration.

gr_gk20a.h uses dbg_session_gk20a, but was missing forward
declaration.

gr_gk20a.h did not include nvgpu.h but it uses preemption types from
that header. Add include.

Change-Id: I2168e2303b55e0d187b816bcb26f37c8af1649ba
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1283717
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
2017-01-27 10:53:25 -08:00
Terje Bergstrom
e52c6ac1f2 gpu: nvgpu: Bump semaphore timeout
Semaphore acquire timeout is configured to half of watchdog timeout.
This is too short, so bump it to 80% of watchdog timeout.

Bug 200261389

Change-Id: Ie906ea3d3520c2e3f547cff7ffbb1e37459e6d2f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1283623
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-26 12:52:55 -08:00
Deepak Nibade
8613119529 gpu: nvgpu: add target refcount for gk20a_wait_for_idle()
API gk20a_wait_for_idle() right now always waits for
0 usage count

But in case railgating is disabled through sysfs,
usage count will never get to 0
Hence in this case we should wait for usage count
of 1

If platform->user_railgate_disabled is set,
keep target usage count of 1, otherwise keep
target usage count as 0

Bug 200260926

Change-Id: I1a80621ca61babbd6566989dc09a7b20670c649c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1291421
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-25 02:41:02 -08:00
Alex Waterman
4feb078717 gpu: nvgpu: Make driver rebind work
Make the GPU bind and rebind operations work when the driver
is idle. This required two changes.

1. Reset the GPU before doing SW init for PCI GPUs. This clears
the SW state which may be stale in the case of a rebind attempt.

2. Cleanup the interrupt enable/disables. Firstly there was one
place where nvgpu would accidentally disable the stalling
interrupt twice when the stalling interrupt and non-stalling
interrupt are the same. Secondly make sure when exiting nvgpu
that the interrupt enable/disables are balanced. Leaving the
interrupt in the -1 disable state means that next time the
driver runs interrupts never quite get enabled.

Bug 1816516

Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1287643
Reviewed-on: http://git-master/r/1287649
(cherry picked from commit aa15af0aae5d0a95a8e765469be4354ab7ddd9f8)
Change-Id: I945e21c1fbb3f096834acf850616b71b2aab9ee3
Reviewed-on: http://git-master/r/1292700
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-24 15:15:22 -08:00
Alex Waterman
efe3266431 gpu: nvgpu: Add GPU reset to XVE
Add a full GPU reset function to the XVE block. This allows
the driver to reset the GPU (except the XVE and XP interfaces)
to clear the GPU's state.

This is necessary for the GPU rebind to work. The state of the
GPU needs to be cleared before the new driver instance can work.

Bug 1816516

Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1287642
Reviewed-on: http://git-master/r/1287648
(cherry picked from commit 7e751c0eb2c0f7d9d0b2020600c33fc8b4381878)
Change-Id: Ie2b721bf1b40acbab34de2436dea4e70d33b5611
Reviewed-on: http://git-master/r/1292698
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-24 15:15:22 -08:00
Alex Waterman
d2b851533b gpu: nvgpu: Use correct class for driver de-init
When removing the driver nodes make sure to use the correct class
to free the dev-node.

Bug 1816516

Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1287641
Reviewed-on: http://git-master/r/1287647
(cherry picked from commit acf97306b4950d8397bb511784b3391a3530ff77)
Change-Id: I983a2106eff6f4839c52a2e16bdd036facb501c0
Reviewed-on: http://git-master/r/1292697
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-24 15:15:22 -08:00
Mihir Thakkar
bbc2342331 gpu: nvgpu: Debug spew for context priority & Gfxp
Prints out Timeslice value, Interleave level, Graphics preemption
mode and compute preempt mode along with chid, tsgid, pid.

Enable it with setting dbg_mask with 8192

Bug 1855710

Change-Id: I60efef9810587f8fedd4e2ba62ba67d06d84faea
Signed-off-by: Mihir Thakkar <mthakkar@nvidia.com>
Reviewed-on: http://git-master/r/1287141
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-24 14:06:06 -08:00
Seema Khowala
16bf1e9416 gpu: nvgpu: Add null check for g->host1x_dev
gk20a_tegra_dump_debug() is set in a platform where host1x support
is not enabled.

Change-Id: Ic57f9081d75be976a092827b253cb2a195d8f16d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1284336
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-24 14:05:54 -08:00
seshendra Gadagottu
8b4aadaadd gpu: nvgpu: restore golden context without bind
Copy and restore golden context correctly with
context header. Removed parallel fecs bind method,
which can cause issues for context in execution.

Also added function pointer to freeing context
header during channel context free.

Bug 1834201

Change-Id: I7962d68338d5144f624375ab81436e86cb31051e
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1275201
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-20 10:54:17 -08:00
Deepak Nibade
d0e3e66885 gpu: nvgpu: compare rounded freq to last value
We right now compare requested value to the last
freq value. Last freq value is always a rounded
value, whereas requested value need not be a
rounded value

Hence it is incorrect to compare requested value
to last freq value

Fix this by comparing rounded value to last_freq

Change-Id: I7c6ea7c4e57105598c9af75efe70016b7fa8038b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1287360
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-20 09:45:19 -08:00
Shardar Shariff Md
a470647ad7 gpu: nvgpu: use soc/tegra/chip-id.h for soc header
The soc tegra headers are unified and moved all the content of
linux/tegra-soc.h to the soc/tegra/chip-id.h to have the
single soc header for Tegra.

Change-Id: I281e19dd3eb1538b8dfbea4eb0779fb64d1fcffa
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1288365
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-20 08:24:01 -08:00
Vijayakumar
54534ee1a9 gpu: nvgpu: pmu version update
bug 200269171

Updating PMU firmware to fix voltage raise when switching mclk to 810mhz
with CLFC and MSCG enabled. The fix is to make sure that clock domain is
not evaluated in CLFC if MSCG has engaged anytime after the previous
evaluation

Change-Id: I2b6979ed3361f47273f2643c27c005deac49dc8b
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1286437
(cherry picked from commit dbfccb42614ec9361628b3c3427a65d3fe908597)
Reviewed-on: http://git-master/r/1287461
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-18 22:26:34 -08:00
Konsta Holtta
bf0a666be0 gpu: nvgpu: fix dev_info typo in refcount tracking
The recently added refcount tracking support had a slight mishap in
refactoring some printks. Fix a typo to make the support compile again
when enabled.

Bug 1826754

Change-Id: Ifd76d644932fa219751db82a0beb3c8482ea68c3
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1285922
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-18 16:47:32 -08:00
Deepak Goyal
bbea338b44 nvgpu: pmu: Update perfmon unit ID for T19x.
update perfmon id for t19x in get_perfmon_id().

JIRA GV11B-30

Change-Id: I7c76b49cc47f8de1e6fa9492e2986830dcff901f
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1284763
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-18 16:47:25 -08:00
Deepak Goyal
a69fa0e96c nvgpu: pmu: Use ops to get PMU queue HEAD/TAIL.
pmu_queue_head() & pmu_queue_tail() are updated
to use gops to include chip specific PMU queue
head/tail registers.

JIRA GV11B-30

Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1283266
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-18 16:46:50 -08:00
Alex Waterman
6e2237ef62 gpu: nvgpu: Use timer API in gk20a code
Use the timers API in the gk20a code instead of Linux specific
API calls.

This also changes the behavior of several functions to wait for
the full timeout for each operation that can timeout. Previously
the timeout was shared across each operation.

Bug 1799159

Change-Id: I2bbed54630667b2b879b56a63a853266afc1e5d8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1273826
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-18 16:46:33 -08:00
Deepak Goyal
eba4aba00c nvgpu: pmu: Add support for new PMU ucode.
-GV11B PMU ucode is added in nvgpu supported
 ucodes.
-PMU INIT msg structure(v4) is added

JIRA GV11B-30

Change-Id: Ifced87b1ca2692c277ae11f562cb36b328da3fe4
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1259274
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-18 16:46:27 -08:00
Seema Khowala
911dcedb48 gpu: nvgpu: support t19x zbc
Added infrastructure for supporting
new zbc features

JIRA GV11B-9

Change-Id: Id8408348759488e8b0393dd89dd0faacfb111f01
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1235525
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-18 16:46:15 -08:00
Deepak Nibade
72f27f7747 gpu: nvgpu: serialize debug session IOCTLs
Hold debug_s->ioctl_lock for all debug session
IOCTLs to prevent multi-threaded user space
IOCTL calls

debug session IOCTL calls are not thread-safe
and hence this serialization is required

Bug 1832267

Change-Id: I847ac951601d4f0093546b592bdb8c8f00185317
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1286436
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-17 10:44:20 -08:00
Deepak Nibade
4942cc4222 gpu: nvgpu: wait for idle in shutdown
In gk20a_pm_shutdown(), we currently do not wait
for IOCTLs or threads in progress and directly
proceed with shutdown sequence

This can cause random hangs during system shutdown

Fix this by calling gk20a_wait_for_idle() after
we disable runtime PM in gk20a_pm_shutdown()

Bug 200260926

Change-Id: I0f06ba9232263fcb09c6e9d246be89deec053d44
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1286522
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-17 09:24:07 -08:00
Mahantesh Kumbar
9c0c4dcf3f gpu: nvgpu: Added lpwr_debug debugfs node
- lpwr_debug node to dump current pstate &
 PG status.

JIRA DNVGPU-165

Change-Id: I8240aea7145c3016946f4322fe0781d78ee2ec73
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1253509
(cherry picked from commit 4852997df5b89aeb8544ed9092ccc9ee8b8c375e)
Reviewed-on: http://git-master/r/1271618
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-17 08:15:13 -08:00
Mahantesh Kumbar
6420f72170 gpu: nvgpu: HAL to get current pstate
- Added HAL support to get current
  pstate from clk_arb

Note - This function is inherently unsafe to call while
arbiter is running arbiter must be blocked
before calling this function

JIRA DNVGPU-165

Change-Id: I4e9f5eba7739280bddd9ee661fd314288c129516
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1286378
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-17 08:15:13 -08:00
Mahantesh Kumbar
efe0758081 gpu: nvgpu: fix pmu->mscg_stat optimization issue
- with help of WRITE_ONCE() & ACCESS_ONCE()
  make sure variable pmu->mscg_stat read/write goes through
  without optimization
- Added WRITE_ONCE() define for kernel-3.18 version & below
  to support backward compatibility

issue: inconsistencies on getting MSCG to trigger consistently in P5
due to a lack of memory barrier around and volatile accesses to the
variable pmu->mscg_stat

JIRA DNVGPU-71

Change-Id: I04d30493d42c52710304dbdfb9cb4a1e9a76f2c0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1252524
(cherry picked from commit 8af7fc68e7ab06a856ba4ef4e44de7336682361b)
Reviewed-on: http://git-master/r/1271614
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-17 08:15:12 -08:00
Deepak Nibade
76dc6659ff gpu: nvgpu: print process name on submit failure
Print process name if we fail submit due to gk20a_busy()
failure

This is helpful in debugging and to know the process name
submitting jobs to nvgpu after system shutdown was
already triggered

Bug 200262275

Change-Id: I34d8c07fc96fd5556afa982bfd56f7f3964449d0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1284113
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2017-01-17 07:11:32 -08:00
seshendra Gadagottu
36cc693ccb gpu: nvgpu: sim: avoid fecs golden context restore
When gpu host is executing a context, there should not be any calls
to fecs that can change the current context in execution. For some
reason legacy fmodels are calling fecs method to golden
context restore while loading golden context for new channel.
This call is not required and should not be called. Only first
time during golden context creation, fecs methods like bind can be
called and it is pretty safe to do.

Bug 1834201

Change-Id: Ia6178e875e3ac37fb1cf10e27976c26b9a02c56f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1284512
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-16 15:54:15 -08:00
Thomas Fleury
f6a634ff24 gpu: nvgpu: use HAL to set TSG timeslice
Setting timeslice for virtualized case was not effective,
because both ioctls NVGPU_TSG_IOCTL_SET_TIMESLICE and
NVGPU_SCHED_IOCTL_TSG_SET_TIMESLICE were calling the
native function to set TSG timeslice.
- Fixed wrapper function to call HAL
- Defined HAL function for "native" set TSG timeslice
- Also, properly update timeout_us in TSG context, in
  virtualized case.

This change also moves the min/max bounds checking for
tsg timeslice into the native function implementation.
There is no sysfs node for these parameters for vgpu,
as RM server is ultimately responsible for this check.

Bug 200263575

Change-Id: Ibceab9427561ad58ec28abfff0c96ca8f592bdb9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1283180
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-16 12:15:23 -08:00
Mahantesh Kumbar
bb5a9e1c6c gpu: nvgpu: PG sysfs update for RPPG/MSCG
- Added sysfs node to control RPPG/MSCG enable/disable
- RPPG is controlled with elpg_enable  node, same node used to
  control ELPG.
- MSCG is controlled with mscg_enable node

JIRA DNVGPU-71

Change-Id: I1a1b33d7425c25c9cfd466f7cabce08f3152326d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1251611
(cherry picked from commit eaf255f2dd3d20c071714dd509a785e9172399bf)
Reviewed-on: http://git-master/r/1274645
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-01-16 04:53:38 -08:00
Mahantesh Kumbar
c8d82d465c gpu: nvgpu: HAL to query LPWR feature support
HAL to query LPWR feautre's RPPG/MSCG support
based on current pstate configured.

JIRA DNVGPU-71

Change-Id: I58a34c6dca68e3eb76e222bd781578bf682eac34
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1283916
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-01-16 04:53:38 -08:00
Peter Boonstoppel
f15a86f265 gpu: nvgpu: Add sysfs nodes for timeslice min/max
The timeslice values that can be selected for a particular channel/tsg
are bounded by a static min/max. This change introduces two sysfs
nodes that allow these bounds to be configured from userspace.

min_timeslice_us
max_timeslice_us

Bug 200251974
Bug 1854791

Change-Id: I5d5a14225eee4090e418c7e43629324114f60768
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1280372
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-12 08:23:56 -08:00
Terje Bergstrom
09dba979a8 gpu: nvgpu: Update patch count after adding
When kernel adds patches to a context, kernel needs to update
the patch count in order for FECS to pick up the new patches.
Previously patching was done only at the context creation 
time. Now patching is used also when changing preemption mode,
but the patches did not take effect due to not updating count.

Update patch count every time we end patching of a context.

Bug 1852094

Change-Id: Ic2150741609d1d1956769e439ce1c5f2edcacb84
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1280424
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-11 12:44:20 -08:00
Alex Waterman
b928f10d37 gpu: nvgpu: Start re-organizing the HW headers
Reorganize the HW headers of gk20a. The headers are moved to a
new directory:

  include/nvgpu/hw/gk20a

And from the code are included like so:

  #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>

This is the first step in reorganizing all of the HW headers for
gm20b, gm206, etc. This is part of a larger effort to re-structure
and make the driver more readable and scalable.

Bug 1799159

Change-Id: Ic151155cbc2e6f75009f2d9d597b364a1bed2c4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1244790
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-11 12:44:14 -08:00
Konsta Holtta
5e68c6e971 gpu: nvgpu: add support for refcount tracking
If enabled, track actions (gets and puts) on channel reference counters.
Dump the most recent actions to syslog when
gk20a_wait_until_counter_is_N gets stuck when closing a channel.
GK20A_CHANNEL_REFCOUNT_TRACKING specifies the size of the action
history. Default is to disable completely, as this has some runtime
overhead.

Bug 1826754

Change-Id: I880b0efe8881044d02ae224c243a51cb6c2db8c1
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1262424
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-11 09:13:43 -08:00
Mahantesh Kumbar
318524ee2f gpu: nvgpu: set PMU "queue full" as debug message
Queue full message is not an error, it informs queue is full
& wait till it gets space in queue to upload pending request.

Bug 200256603

Change-Id: I14f4196b391cd54e1b9616f0555a5ce0856af428
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1260494
(cherry picked from commit e7360fb52b2030c9c68aa5ed06ecd7c32b47a8c5)
Reviewed-on: http://git-master/r/1271619
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-10 20:16:10 -08:00
Mahantesh Kumbar
7552780739 gpu: nvgpu: pg mscg state update
- Added mscg_transition_state to know
 mscg allow/disallow status
- reused ELPG state transition defines
 for mscg state transition

JIRA DNVGPU-71

Change-Id: Ie0214a174ceecf7e97a1086f53fd965b0b655d14
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1253508
(cherry picked from commit 726dde9cff1da38525518a91e756598a5ab71f73)
Reviewed-on: http://git-master/r/1271617
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-10 20:16:05 -08:00
Mahantesh Kumbar
d8049d384f gpu: nvgpu: pmu->pmu_state update
- set pmu->pmu_state to PMU_STATE_ELPG_BOOTED
 only for ELPG after PMU_STATE_ELPG_BOOTING
 state

Bug N/A

Change-Id: I08480e2afd5a5050a903327b91e43b25780cdaf8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1254429
(cherry picked from commit d68f4f91796d1d98dbc1b5b24d526fe2e487966f)
Reviewed-on: http://git-master/r/1271616
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-10 20:15:59 -08:00
Lakshmanan M
8d712cd235 gpu: nvgpu: Add thermal alarm notification for UMD
Added the thermal alarm notification handling for UMD

JIRA DNVGPU-130
Bug 200231080

Change-Id: I034c7b35a18a091ef7659ff992f1950576623cad
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1251760
(cherry picked from commit 9e66f2e2f7fbcab29e25c976c1d5fa29671afcd0)
Reviewed-on: http://git-master/r/1282084
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-10 15:23:36 -08:00
Mahantesh Kumbar
f3e0dba8bf gpu: nvgpu: pg stat read update
- Added struct pmu_pg_stats_data to extract
data from multiple version of pmu pg statistics

- Added pmu_pg_stats_v2 interface to fetch
PG statistics data from PMU

- Added MSCG debugfs node to read mscg
statistics from PMU.

- Added pmu_elpg_statistics HAL support for
  gp106 PG statistics read.

- Made changes to gp104/gp106
  pmu_elpg_statistics HAL to support
  for struct pmu_pg_stats_data

JIRA DNVGPU-165

Change-Id: I2b9e89c0fae90deb45006c4478170b9a97b56603
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1252798
(cherry picked from commit 3c073b15fd991db8d65b3171b02c161294be40cd)
Reviewed-on: http://git-master/r/1271615
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-10 09:24:06 -08:00
Lakshmanan M
8a63a431c4 gpu: nvgpu: Add thermal alert limit IOCTL for UMD
Added the thermal alert lmit IOCTL for UMD

JIRA DNVGPU-130
Bug 200231080

Change-Id: I4a84157d90b12b576fa144567a3bdd5d39f5278e
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1249483
(cherry picked from commit d3458008cc3dd98d3a51841b6ed8cea1aed9eb89)
Reviewed-on: http://git-master/r/1253457
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-01-10 03:54:56 -08:00
Lakshmanan M
eaeb5ff20f gpu: nvgpu: Add thermal alert event handling
* Added the thermal alert event handling
* Added the thermal alert event PMU RPC

JIRA DNVGPU-130
Bug 200231080

Change-Id: If5ff2704e5aa6ad2f25123f72c3049a311dae5dc
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1248964
(cherry picked from commit 1850e5a9b9dfa2f9df634e2f284ab282ad9f7fc8)
Reviewed-on: http://git-master/r/1253452
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-10 03:54:56 -08:00
Terje Bergstrom
1c9b8c7868 gpu: nvgpu: Move GPFIFO to sysmem
Kickoff latencies when GPFIFO is in vidmem grow significantly as
function of number of GPFIFO entries. Move GPFIFO to sysmem to
improve kickoff latency.

Bug 1848369

Change-Id: Ie95d10df26b4f1370f7250a8fbf0f7ef0211df32
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry-picked from commit 897cb579a759bbe8455ce368413979e91eb0d475)
Reviewed-on: http://git-master/r/1281564
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-09 12:33:22 -08:00
Alex Waterman
6df3992b60 gpu: nvgpu: Move allocators to common/mm/
Move the GPU allocators to common/mm/ since the allocators are common
code across all GPUs. Also rename the allocator code to move away from
gk20a_ prefixed structs and functions.

This caused one issue with the nvgpu_alloc() and nvgpu_free() functions.
There was a function for allocating either with kmalloc() or vmalloc()
depending on the size of the allocation. Those have now been renamed to
nvgpu_kalloc() and nvgpu_kfree().

Bug 1799159

Change-Id: Iddda92c013612bcb209847084ec85b8953002fa5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1274400
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-09 12:33:16 -08:00
David Nieto
1526670f4a gpu: nvgpu: Add support for alarms in arbiter
Pass flags as mask in event initialization

JIRA: DNVGPU-189$

Change-Id: Ied22a585a8f59f44e577bc678f8cef380432c9a2
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1252474
(cherry picked from commit 56fa34b8ac0ebafaf09a8760bec6200adf9f3c39)
Reviewed-on: http://git-master/r/1280886
GVS: Gerrit_Virtual_Submit
Tested-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-06 09:14:05 -08:00
Terje Bergstrom
e3e2786567 gpu: nvgpu: Do not access NULL pointer dev
In gk20a_busy() we check if dev is NULL and return -ENODEV if so. But
before that we've already dereferenced dev by passing it to
get_gk20a(). Defer call to get_gk20a() until after the NULL check.

Bug 200192125

Change-Id: I943a9e96d13ff8cb4333fe20a941c8e95d159a66
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1280349
GVS: Gerrit_Virtual_Submit
2017-01-06 09:13:59 -08:00
Deepak Nibade
0b9a4411aa gpu: nvgpu: fix out-of-bound access on gr->map_tiles
Fix slab-out-of-bounds issue reported by KASAN

[   28.464077] BUG: KASAN: slab-out-of-bounds in
gr_gk20a_init_map_tiles+0x624/0x708 at addr ffffffc1a098ee01
...
[   28.503241] INFO: Allocated in gr_gk20a_init_map_tiles+0x2dc/0x708
age=11 cpu=5 pid=1

out-of-bound access from below 3 stacks :
[1]
[   28.782886] [<ffffffc0007d5f64>] gr_gk20a_init_map_tiles+0x624/0x708
[   28.789228] [<ffffffc0007eadf0>] gk20a_init_gr_support+0x2d0/0xeb0
[   28.795397] [<ffffffc00079d9c8>]
gk20a_pm_finalize_poweron+0x738/0xd10

[2]
[   29.268070] [<ffffffc0007d618c>] gr_gk20a_zcull_init_hw+0x144/0x730
[   29.274329] [<ffffffc0007d6a00>] gk20a_init_gr_setup_hw+0x288/0x1530
[   29.280677] [<ffffffc0007eac6c>] gk20a_init_gr_support+0x14c/0xeb0
[   29.286938] [<ffffffc00079d9c8>]
gk20a_pm_finalize_poweron+0x738/0xd10

[3]
[   50.076223] [<ffffffc000d1df14>]
gr_gk20a_setup_rop_mapping+0x5e4/0x2018
[   50.082913] [<ffffffc000d2559c>] gr_gk20a_init_fs_state+0x80c/0x1028
[   50.089259] [<ffffffc000ddcbc8>] gr_gm20b_init_fs_state+0xc8/0x960
[   50.095430] [<ffffffc000e413f8>] gr_gp10b_init_fs_state+0x5c0/0x5d8
[   50.101687] [<ffffffc000d2ed30>] gk20a_init_gr_setup_hw+0x1b48/0x2418
[   50.108115] [<ffffffc000d50bc0>] gk20a_init_gr_support+0x19e0/0x1ab0
[   50.114457] [<ffffffc000cc7af8>]
gk20a_pm_finalize_poweron+0xd20/0x1558

Fix this by adding below
- allocate gr->map_tiles[] with size of (num_gpc * num_tpc_per_gpc)
  intead of num_gpc
- add new static API gr_gk20a_get_map_tile_count() which returns
  tile count for given index, and returns 0 for out-of-bounds access

Bug 200257557

Change-Id: If572837ffb661f92a21be5ce855d0146b2609cb0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1279411
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-06 09:13:58 -08:00
David Nieto
5711e2b1f7 gpu: nvgpu: remove default verbose in pbus isr
And reduce pri timeout to match PCIE specs

bug 200246808

Change-Id: I0225ae964b5635665fe774c43f773d0ce86650ab
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1264179
(cherry picked from commit 1c3dbf8324b7ec5d06bd0e57e7deee9a1c8e9411)
Reviewed-on: http://git-master/r/1280328
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-01-04 15:54:01 -08:00