mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
124 lines
4.0 KiB
C
124 lines
4.0 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <stdlib.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include <unit/io.h>
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#include <unit/unit.h>
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#include <nvgpu/types.h>
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#include <nvgpu/engine_status.h>
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#include "../nvgpu-fifo-common.h"
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#include "nvgpu-engine-status.h"
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#define assert(cond) unit_assert(cond, goto done)
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#define NUM_CTXSW_STATUS 6
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#define NUM_ID_TYPES 3
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#define NUM_NEXT_ID_TYPES 3
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int test_engine_status(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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int ret = UNIT_FAIL;
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struct nvgpu_engine_status_info status;
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const u32 ctxsw_status[NUM_CTXSW_STATUS] = {
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NVGPU_CTX_STATUS_INVALID,
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NVGPU_CTX_STATUS_VALID,
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NVGPU_CTX_STATUS_CTXSW_LOAD,
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NVGPU_CTX_STATUS_CTXSW_SAVE,
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NVGPU_CTX_STATUS_CTXSW_SWITCH,
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U32(~0),
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};
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const u32 id_types[NUM_ID_TYPES] = {
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ENGINE_STATUS_CTX_ID_TYPE_CHID,
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ENGINE_STATUS_CTX_ID_TYPE_TSGID,
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ENGINE_STATUS_CTX_ID_TYPE_INVALID,
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};
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const u32 next_id_types[NUM_NEXT_ID_TYPES] = {
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ENGINE_STATUS_CTX_NEXT_ID_TYPE_CHID,
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ENGINE_STATUS_CTX_NEXT_ID_TYPE_TSGID,
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ENGINE_STATUS_CTX_NEXT_ID_TYPE_INVALID,
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};
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int i;
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for (i = 0; i < NUM_CTXSW_STATUS; i++)
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{
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status.ctxsw_status = ctxsw_status[i];
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assert(nvgpu_engine_status_is_ctxsw_switch(&status) ==
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(ctxsw_status[i] == NVGPU_CTX_STATUS_CTXSW_SWITCH));
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assert(nvgpu_engine_status_is_ctxsw_load(&status) ==
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(ctxsw_status[i] == NVGPU_CTX_STATUS_CTXSW_LOAD));
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assert(nvgpu_engine_status_is_ctxsw_save(&status) ==
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(ctxsw_status[i] == NVGPU_CTX_STATUS_CTXSW_SAVE));
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assert(nvgpu_engine_status_is_ctxsw(&status) ==
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((ctxsw_status[i] == NVGPU_CTX_STATUS_CTXSW_SWITCH) ||
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(ctxsw_status[i] == NVGPU_CTX_STATUS_CTXSW_LOAD) ||
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(ctxsw_status[i] == NVGPU_CTX_STATUS_CTXSW_SAVE)));
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assert(nvgpu_engine_status_is_ctxsw_invalid(&status) ==
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(ctxsw_status[i] == NVGPU_CTX_STATUS_INVALID));
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assert(nvgpu_engine_status_is_ctxsw_valid(&status) ==
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(ctxsw_status[i] == NVGPU_CTX_STATUS_VALID));
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}
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for (i = 0; i < NUM_ID_TYPES; i++)
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{
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u32 ctx_id, ctx_type;
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status.ctx_id = i;
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status.ctx_id_type = id_types[i];
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status.ctx_next_id = 0xcafe;
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status.ctx_next_id_type = 0xcafe;
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assert(nvgpu_engine_status_is_ctx_type_tsg(&status) ==
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(id_types[i] == ENGINE_STATUS_CTX_ID_TYPE_TSGID));
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nvgpu_engine_status_get_ctx_id_type(&status,
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&ctx_id, &ctx_type);
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assert(ctx_id == status.ctx_id);
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assert(ctx_type == status.ctx_id_type);
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}
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for (i = 0; i < NUM_NEXT_ID_TYPES; i++)
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{
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u32 ctx_next_id, ctx_next_type;
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status.ctx_id = 0xcafe;
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status.ctx_id_type = 0xcafe;
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status.ctx_next_id = i;
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status.ctx_next_id_type = next_id_types[i];
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assert(nvgpu_engine_status_is_next_ctx_type_tsg(&status) ==
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(next_id_types[i] ==
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ENGINE_STATUS_CTX_NEXT_ID_TYPE_TSGID));
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nvgpu_engine_status_get_next_ctx_id_type(&status,
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&ctx_next_id, &ctx_next_type);
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assert(ctx_next_id == status.ctx_next_id);
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assert(ctx_next_type == status.ctx_next_id_type);
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}
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ret = UNIT_SUCCESS;
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done:
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return ret;
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}
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