mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
To add GL/VK support for shader debugging via the SM trap handler functionality, a write operation to the following PRI registers need to be allowed in all chips (ga10b, gv11b, gm20b, gp10b): - NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL - NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED - NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0 - NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK - NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK In this patch, we are adding the above registers into allowlist, if they were absent. Note that these registers included only in non-safety using CONFIG_NVGPU_SET_FALCON_ACCESS_MAP flag. Bug 3642131 Change-Id: I5f62731944b6b3e059afa80a491c3cf5c3656f60 Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2715799 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Christopher Lentini <clentini@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Christopher Lentini <clentini@nvidia.com>