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gpu: nvgpu: add additional registers to allowlist

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To add GL/VK support for shader debugging via the SM trap handler
functionality, a write operation to the following PRI registers need to
be allowed in all chips (ga10b, gv11b, gm20b, gp10b):

- NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL
- NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED
- NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0
- NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK
- NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK

In this patch, we are adding the above registers into allowlist, if they
were absent. Note that these registers included only in non-safety using
CONFIG_NVGPU_SET_FALCON_ACCESS_MAP flag.

Bug 3642131

Change-Id: I5f62731944b6b3e059afa80a491c3cf5c3656f60
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2715799
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Christopher Lentini <clentini@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Christopher Lentini <clentini@nvidia.com>
This commit is contained in:
Rajesh Devaraj
2022-05-20 09:51:35 +00:00
committed by mobile promotions
parent 658f83ca48
commit 019bee2174
3 changed files with 10 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c
View File

@@ -88,6 +88,7 @@ void ga10b_gr_init_get_access_map(struct gk20a *g,
0x418380, /* gr_pri_gpcs_rasterarb_line_class */
0x418800, /* gr_pri_gpcs_setup_debug */
0x418830, /* gr_pri_gpcs_setup_debug_z_gamut_offset */
0x4188b0, /* gr_pri_gpcs_mmu_debug_ctrl */
0x4188fc, /* gr_pri_gpcs_zcull_ctx_debug */
0x418e00, /* gr_pri_gpcs_swdx_config */
0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */
@@ -114,9 +115,11 @@ void ga10b_gr_init_get_access_map(struct gk20a *g,
0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */
0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */
0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */
0x419b48, /* gr_pri_gpcs_tpcs_sm_sch_macro_sched */
0x419ba4, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */
0x419e84, /* gr_pri_gpcs_tpcs_sms_dbgr_control0 */
0x419ea8, /* gr_pri_gpcs_tpcs_sms_hww_warp_esr_report_mask */
0x419eac, /* gr_pri_gpcs_tpcs_sms_hww_global_esr_report_mask */
};
size_t array_size;

4
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
View File

@@ -88,6 +88,7 @@ void gm20b_gr_init_get_access_map(struct gk20a *g,
0x418380, /* gr_pri_gpcs_rasterarb_line_class */
0x418800, /* gr_pri_gpcs_setup_debug */
0x418830, /* gr_pri_gpcs_setup_debug_z_gamut_offset */
0x4188b0, /* gr_pri_gpcs_mmu_debug_ctrl */
0x4188fc, /* gr_pri_gpcs_zcull_ctx_debug */
0x418e00, /* gr_pri_gpcs_swdx_config */
0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */
@@ -115,6 +116,9 @@ void gm20b_gr_init_get_access_map(struct gk20a *g,
0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */
0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */
0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */
0x419e44, /* gr_pri_gpcs_tpcs_sms_hww_warp_esr_report_mask */
0x419e4c, /* gr_pri_gpcs_tpcs_sms_hww_global_esr_report_mask */
0x419eac, /* gr_pri_gpcs_tpcs_sm_sch_macro_sched */
0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */
};
size_t array_size;

3
drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c
View File

@@ -60,6 +60,7 @@ void gv11b_gr_init_get_access_map(struct gk20a *g,
0x418380, /* gr_pri_gpcs_rasterarb_line_class */
0x418800, /* gr_pri_gpcs_setup_debug */
0x418830, /* gr_pri_gpcs_setup_debug_z_gamut_offset */
0x4188b0, /* gr_pri_gpcs_mmu_debug_ctrl */
0x4188fc, /* gr_pri_gpcs_zcull_ctx_debug */
0x418e00, /* gr_pri_gpcs_swdx_config */
0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */
@@ -86,9 +87,11 @@ void gv11b_gr_init_get_access_map(struct gk20a *g,
0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */
0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */
0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */
0x419b48, /* gr_pri_gpcs_tpcs_sm_sch_macro_sched */
0x419ba4, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */
0x419e84, /* gr_pri_gpcs_tpcs_sms_dbgr_control0 */
0x419ea8, /* gr_pri_gpcs_tpcs_sms_hww_warp_esr_report_mask */
0x419eac, /* gr_pri_gpcs_tpcs_sms_hww_global_esr_report_mask */
};
size_t array_size;