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git://nv-tegra.nvidia.com/linux-nvgpu.git
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6885071c64
- The hardware is designed in such a way that if GR engine is not out of reset, it still takes clock. - This causes ELCG feature to not engage correctly. - So for iGPU, SW should bring all supported GR engines out of reset during gpu boot, if MIG feature is not enabled. - This will help low power feature like elcg to engage correctly and improve dynamic power savings. - For dGPU, all GRs are out of reset by default by dev init. Bug 200778542 Change-Id: I5f3519f73b4aaf1804fd112f28fe980f58181cd8 Signed-off-by: Divya <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2613718 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
91 lines
2.3 KiB
C
91 lines
2.3 KiB
C
/*
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* GK20A Master Control
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*
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* Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/device.h>
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#include <nvgpu/mc.h>
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int nvgpu_mc_reset_units(struct gk20a *g, u32 units)
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{
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int err;
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err = g->ops.mc.enable_units(g, units, false);
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if (err != 0) {
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nvgpu_log(g, gpu_dbg_info, "Unit disable failed");
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return err;
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}
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err = g->ops.mc.enable_units(g, units, true);
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if (err != 0) {
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nvgpu_log(g, gpu_dbg_info, "Unit disable failed");
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return err;
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}
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return 0;
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}
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int nvgpu_mc_reset_dev(struct gk20a *g, const struct nvgpu_device *dev)
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{
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int err = 0;
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if (g->ops.mc.enable_dev == NULL) {
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goto fail;
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}
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err = g->ops.mc.enable_dev(g, dev, false);
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if (err != 0) {
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nvgpu_device_dump_dev(g, dev);
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goto fail;
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}
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err = g->ops.mc.enable_dev(g, dev, true);
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if (err != 0) {
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nvgpu_device_dump_dev(g, dev);
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goto fail;
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}
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fail:
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return err;
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}
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int nvgpu_mc_reset_devtype(struct gk20a *g, u32 devtype)
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{
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int err;
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err = g->ops.mc.enable_devtype(g, devtype, false);
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if (err != 0) {
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nvgpu_log(g, gpu_dbg_info, "Devtype:%u disable failed",
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devtype);
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return err;
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}
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err = g->ops.mc.enable_devtype(g, devtype, true);
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if (err != 0) {
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nvgpu_log(g, gpu_dbg_info, "Devtype:%u enable failed",
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devtype);
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return err;
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}
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return 0;
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}
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