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4c2e65c60b
JIRA DNVGPU-123 Change-Id: Ia28db5d645aa431f11dc8720bf1d08e6d756e20f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1227670 (cherry picked from commit 2c7f89ceef3f9173fefa44b1a959345744e66536) Reviewed-on: http://git-master/r/1244659 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
121 lines
3.2 KiB
C
121 lines
3.2 KiB
C
/*
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* general p state infrastructure
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ctrlvolt_h_
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#define _ctrlvolt_h_
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#define CTRL_VOLT_VOLT_RAIL_MAX_RAILS \
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CTRL_BOARDOBJGRP_E32_MAX_OBJECTS
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#include "ctrlperf.h"
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#include "ctrlboardobj.h"
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#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04
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#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8)
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#define CTRL_VOLT_DOMAIN_INVALID 0x00
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#define CTRL_VOLT_DOMAIN_LOGIC 0x01
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#define CLK_PROG_VFE_ENTRY_LOGIC 0x00
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#define CLK_PROG_VFE_ENTRY_SRAM 0x01
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/*
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* Macros for Voltage Domain HAL.
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*/
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#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00
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#define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL 0x01
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/*
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* Macros for Voltage Domains.
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*/
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#define CTRL_VOLT_DOMAIN_INVALID 0x00
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#define CTRL_VOLT_DOMAIN_LOGIC 0x01
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#define CTRL_VOLT_DOMAIN_SRAM 0x02
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/*!
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* Special value corresponding to an invalid Voltage Rail Index.
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*/
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#define CTRL_VOLT_RAIL_INDEX_INVALID \
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CTRL_BOARDOBJ_IDX_INVALID
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/*!
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* Special value corresponding to an invalid Voltage Device Index.
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*/
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#define CTRL_VOLT_DEVICE_INDEX_INVALID \
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CTRL_BOARDOBJ_IDX_INVALID
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/*!
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* Special value corresponding to an invalid Voltage Policy Index.
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*/
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#define CTRL_VOLT_POLICY_INDEX_INVALID \
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CTRL_BOARDOBJ_IDX_INVALID
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enum nv_pmu_pmgr_pwm_source {
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NV_PMU_PMGR_PWM_SOURCE_INVALID = 0,
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NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0 = 4,
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NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1,
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NV_PMU_PMGR_PWM_SOURCE_RSVD_0 = 7,
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NV_PMU_PMGR_PWM_SOURCE_RSVD_1 = 8,
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};
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/*!
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* Macros for Voltage Device Types.
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*/
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#define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00
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#define CTRL_VOLT_DEVICE_TYPE_PWM 0x03
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/*
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* Macros for Volt Device Operation types.
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*/
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#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00
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#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01
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#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02
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#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03
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/*!
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* Macros for Voltage Domains.
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*/
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#define CTRL_VOLT_DOMAIN_INVALID 0x00
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#define CTRL_VOLT_DOMAIN_LOGIC 0x01
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#define CTRL_VOLT_DOMAIN_SRAM 0x02
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/*!
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* Macros for Volt Policy types.
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*
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* Virtual VOLT_POLICY types are indexed starting from 0xFF.
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*/
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#define CTRL_VOLT_POLICY_TYPE_INVALID 0x00
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#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01
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#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02
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#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03
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#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFE
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#define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFF
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/*!
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* Macros for Volt Policy Client types.
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*/
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#define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00
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#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01
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struct ctrl_volt_volt_rail_list_item {
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u8 rail_idx;
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u32 voltage_uv;
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};
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struct ctrl_volt_volt_rail_list {
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u8 num_rails;
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struct ctrl_volt_volt_rail_list_item
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rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
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};
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#endif
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