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e486ff45d0
nvlink alt_clk switch defaults to slowclk; the init value of register field is slowclk. So we need not program the register field 'clk_alt_switchfinalsel'. Also the code lines were not taking effect as the value is not written back to the register. JIRA NVGPU-966 Change-Id: I75904e94a8e113c17fb3bf8c414174c549ad893e Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795050 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>