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0957229524
nvgpu_gr_init_fs_state is right now defined in common.gr.gr unit This API also needs to be called from common.gr.obj_ctx unit so obj_ctx unit depends on gr unit for this. common.gr.gr unit already depends on common.gr.obj_ctx for context initialization. So this causes a circular dependency Fix this by moving this API to new standalone unit common.gr.fs_state Rename it to nvgpu_gr_fs_state_init Jira NVGPU-1887 Change-Id: I88ca8e1a7bc3c544459462493116f95d92b9ab01 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2090496 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/gr/gr.h>
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#include <nvgpu/gr/config.h>
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u32 nvgpu_gr_gpc_offset(struct gk20a *g, u32 gpc)
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{
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u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
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u32 gpc_offset = gpc_stride * gpc;
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return gpc_offset;
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}
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u32 nvgpu_gr_tpc_offset(struct gk20a *g, u32 tpc)
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{
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u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g,
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GPU_LIT_TPC_IN_GPC_STRIDE);
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u32 tpc_offset = tpc_in_gpc_stride * tpc;
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return tpc_offset;
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}
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int nvgpu_gr_suspend(struct gk20a *g)
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{
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int ret = 0;
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nvgpu_log_fn(g, " ");
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ret = g->ops.gr.init.wait_empty(g);
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if (ret != 0) {
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return ret;
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}
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/* Disable fifo access */
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g->ops.gr.init.fifo_access(g, false);
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/* disable gr intr */
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g->ops.gr.intr.enable_interrupts(g, false);
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/* disable all exceptions */
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g->ops.gr.intr.enable_exceptions(g, g->gr.config, false);
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nvgpu_gr_flush_channel_tlb(g);
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g->gr.initialized = false;
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nvgpu_log_fn(g, "done");
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return ret;
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}
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/* invalidate channel lookup tlb */
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void nvgpu_gr_flush_channel_tlb(struct gk20a *g)
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{
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nvgpu_spinlock_acquire(&g->gr.ch_tlb_lock);
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(void) memset(g->gr.chid_tlb, 0,
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sizeof(struct gr_channel_map_tlb_entry) *
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GR_CHANNEL_MAP_TLB_SIZE);
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nvgpu_spinlock_release(&g->gr.ch_tlb_lock);
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}
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/* Wait until GR is initialized */
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void nvgpu_gr_wait_initialized(struct gk20a *g)
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{
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NVGPU_COND_WAIT(&g->gr.init_wq, g->gr.initialized, 0U);
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}
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