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git://nv-tegra.nvidia.com/linux-nvgpu.git
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b368dc48b3
- Create nvlink_bios.c/.h files to separate out nvlink related bios code. - Create bios_sw_<chip speciific>.c/.h files to separate out chips specific bios code. - Create hal files for bios under hal/bios/ and move hardware specific code there. - Move hardware accessing hal files from common/top to hal/top JIRA NVGPU-2071 Change-Id: Ia466f1cd8947540b07b237e891312123df2c6b46 Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2107371 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
76 lines
2.4 KiB
C
76 lines
2.4 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "bios_sw_tu104.h"
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#include "bios_sw_gp106.h"
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#define NV_DEVINIT_VERIFY_TIMEOUT_MS 1000U
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#define NV_DEVINIT_VERIFY_TIMEOUT_DELAY_US 10U
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_MASK \
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0xFFU
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED \
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0xFFU
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int tu104_bios_verify_devinit(struct gk20a *g)
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{
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struct nvgpu_timeout timeout;
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u32 val;
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u32 aon_secure_scratch_reg;
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int err;
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err = nvgpu_timeout_init(g, &timeout, NV_DEVINIT_VERIFY_TIMEOUT_MS,
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NVGPU_TIMER_CPU_TIMER);
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if (err != 0) {
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return err;
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}
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do {
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aon_secure_scratch_reg = g->ops.bios.get_aon_secure_scratch_reg(g, 0);
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val = nvgpu_readl(g, aon_secure_scratch_reg);
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val &= NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_MASK;
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if (val == NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED) {
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nvgpu_log_info(g, "devinit complete");
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return 0;
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}
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nvgpu_udelay(NV_DEVINIT_VERIFY_TIMEOUT_DELAY_US);
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} while (nvgpu_timeout_expired(&timeout) == 0);
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return -ETIMEDOUT;
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}
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int tu104_bios_init(struct gk20a *g)
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{
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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return 0;
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}
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return gp106_bios_init(g);
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}
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