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b2980b0c22
Change following ltc hal prototype from: int (*determine_L2_size_bytes)(struct gk20a *gk20a); to u64 (*determine_L2_size_bytes)(struct gk20a *gk20a); JIRA NVGPU-3422 Change-Id: I53cbd7f37cad3c6851e3c5b46af6cdc04013d690 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2119996 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
79 lines
2.3 KiB
C
79 lines
2.3 KiB
C
/*
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* GP10B L2
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/ltc.h>
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#include <nvgpu/log.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/hw/gp10b/hw_ltc_gp10b.h>
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#include "ltc_gm20b.h"
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#include "ltc_gp10b.h"
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u64 gp10b_determine_L2_size_bytes(struct gk20a *g)
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{
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u32 tmp;
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u64 ret;
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nvgpu_log_fn(g, " ");
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tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_info_1_r());
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ret = (u64)g->ltc->ltc_count *
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ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(tmp) * 1024U *
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(u64)ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(tmp);
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nvgpu_log(g, gpu_dbg_info, "L2 size: %llu\n", ret);
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nvgpu_log_fn(g, "done");
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return ret;
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}
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void gp10b_ltc_init_fs_state(struct gk20a *g)
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{
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gm20b_ltc_init_fs_state(g);
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gk20a_writel(g, ltc_ltca_g_axi_pctrl_r(),
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ltc_ltca_g_axi_pctrl_user_sid_f(g->ltc_streamid));
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}
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void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled)
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{
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u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f();
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u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r());
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if (enabled) {
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/* bypass disabled (normal caching ops) */
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reg &= ~reg_f;
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} else {
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/* bypass enabled (no caching) */
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reg |= reg_f;
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}
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nvgpu_writel_check(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg);
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}
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