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git://nv-tegra.nvidia.com/linux-nvgpu.git
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f07d933076
Move chip specific mc code from common/mc to hal/mc. Replace gk20a_readl/writel with nvgpu_readl/writel Replace 0xFFFFFFFFU with U32_MAX hash define Change local variable names to fix checkpatch errors/warnings Change BUG to WARN Move defines to header files Create new defines for hard coded delays JIRA NVGPU-2041 Change-Id: I3594121a81da37ef58c47e87c45e96441e4cf8c7 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2085268 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
69 lines
2.9 KiB
C
69 lines
2.9 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_MC_TU104_H
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#define NVGPU_MC_TU104_H
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#include <nvgpu/types.h>
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#define MAX_INTR_TOP_REGS (2U)
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#define NV_CPU_INTR_SUBTREE_TO_TOP_IDX(i) ((i) / 32U)
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#define NV_CPU_INTR_SUBTREE_TO_TOP_BIT(i) ((i) % 32U)
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#define NV_CPU_INTR_SUBTREE_TO_LEAF_REG0(i) ((i)*2U)
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#define NV_CPU_INTR_SUBTREE_TO_LEAF_REG1(i) (((i)*2U) + 1U)
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#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i) ((i) / 32U)
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#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(i) ((i) % 32U)
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#define NV_CPU_INTR_GPU_VECTOR_TO_SUBTREE(i) ((NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2U)
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#define NV_CPU_INTR_TOP_NONSTALL_SUBTREE 0U
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struct gk20a;
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void intr_tu104_leaf_en_set(struct gk20a *g, u32 leaf_reg_index,
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u32 leaf_reg_bit);
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void intr_tu104_leaf_en_clear(struct gk20a *g, u32 leaf_reg_index,
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u32 leaf_reg_bit);
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void intr_tu104_top_en_set(struct gk20a *g, u32 top_reg_index,
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u32 top_reg_bit);
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void intr_tu104_vector_en_set(struct gk20a *g, u32 intr_vector);
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void intr_tu104_vector_en_clear(struct gk20a *g, u32 intr_vector);
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bool intr_tu104_vector_intr_pending(struct gk20a *g, u32 intr_vector);
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void intr_tu104_intr_clear_leaf_vector(struct gk20a *g, u32 intr_vector);
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void intr_tu104_mask(struct gk20a *g);
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void intr_tu104_enable(struct gk20a *g);
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u32 intr_tu104_stall(struct gk20a *g);
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void intr_tu104_stall_pause(struct gk20a *g);
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void intr_tu104_stall_resume(struct gk20a *g);
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u32 intr_tu104_nonstall(struct gk20a *g);
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void intr_tu104_nonstall_pause(struct gk20a *g);
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void intr_tu104_nonstall_resume(struct gk20a *g);
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u32 intr_tu104_isr_nonstall(struct gk20a *g);
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bool intr_tu104_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0);
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void intr_tu104_log_pending_intrs(struct gk20a *g);
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void mc_tu104_fbpa_isr(struct gk20a *g);
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void mc_tu104_ltc_isr(struct gk20a *g);
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#endif /* NVGPU_MC_TU104_H */
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