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gpu: nvgpu: move chip specific mc to hal

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Move chip specific mc code from common/mc to hal/mc.
Replace gk20a_readl/writel with nvgpu_readl/writel
Replace 0xFFFFFFFFU with U32_MAX hash define
Change local variable names to fix checkpatch errors/warnings
Change BUG to WARN
Move defines to header files
Create new defines for hard coded delays

JIRA NVGPU-2041

Change-Id: I3594121a81da37ef58c47e87c45e96441e4cf8c7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085268
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-03-29 13:37:13 -07:00
committed by mobile promotions
parent 191aeb5cf8
commit f07d933076
19 changed files with 196 additions and 194 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/Makefile
View File

@@ -45,11 +45,6 @@ nvgpu-y += \
common/top/top_gp10b.o \
common/top/top_gv100.o \
common/mc/mc.o \
common/mc/mc_gm20b.o \
common/mc/mc_gp10b.o \
common/mc/mc_gv11b.o \
common/mc/mc_gv100.o \
common/mc/mc_tu104.o \
common/sync/channel_sync.o \
common/sync/channel_sync_semaphore.o \
common/sync/sema_cmdbuf_gk20a.o \
@@ -163,6 +158,11 @@ nvgpu-y += \
common/nvlink/nvlink.o \
common/nvlink/nvlink_gv100.o \
common/nvlink/nvlink_tu104.o \
hal/mc/mc_gm20b.o \
hal/mc/mc_gp10b.o \
hal/mc/mc_gv11b.o \
hal/mc/mc_gv100.o \
hal/mc/mc_tu104.o \
hal/bus/bus_gk20a.o \
hal/bus/bus_gm20b.o \
hal/bus/bus_gp10b.o \

10
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -189,10 +189,6 @@ srcs += common/sim.c \
common/fifo/pbdma_status.c \
common/fifo/userd.c \
common/mc/mc.c \
common/mc/mc_gm20b.c \
common/mc/mc_gp10b.c \
common/mc/mc_gv11b.c \
common/mc/mc_gv100.c \
common/boardobj/boardobj.c \
common/boardobj/boardobjgrp.c \
common/boardobj/boardobjgrpmask.c \
@@ -284,7 +280,6 @@ srcs += common/sim.c \
gv100/gr_gv100.c \
gv100/hal_gv100.c \
gv100/clk_gv100.c \
common/mc/mc_tu104.c \
tu104/bios_tu104.c \
tu104/ecc_tu104.c \
tu104/fbpa_tu104.c \
@@ -294,6 +289,11 @@ srcs += common/sim.c \
tu104/hal_tu104.c \
tu104/sec2_tu104.c \
tu104/func_tu104.c \
hal/mc/mc_gm20b.c \
hal/mc/mc_gp10b.c \
hal/mc/mc_gv11b.c \
hal/mc/mc_gv100.c \
hal/mc/mc_tu104.c \
hal/bus/bus_gk20a.c \
hal/bus/bus_gm20b.c \
hal/bus/bus_gp10b.c \

2
drivers/gpu/nvgpu/common/mc/mc.c
View File

@@ -32,7 +32,7 @@ u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev)
{
u32 val = __nvgpu_readl(g, mc_boot_0_r());
if (val != 0xffffffffU) {
if (val != U32_MAX) {
if (arch != NULL) {
*arch = mc_boot_0_architecture_v(val) <<

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -41,6 +41,7 @@
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/setup.h>
#include "hal/mc/mc_gm20b.h"
#include "hal/bus/bus_gm20b.h"
#include "hal/bus/bus_gk20a.h"
#include "hal/priv_ring/priv_ring_gm20b.h"
@@ -71,7 +72,6 @@
#include "common/ptimer/ptimer_gk20a.h"
#include "common/netlist/netlist_gm20b.h"
#include "common/mc/mc_gm20b.h"
#include "common/perf/perf_gm20b.h"
#include "common/pmu/pmu_gk20a.h"
#include "common/pmu/pmu_gm20b.h"

4
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -42,6 +42,8 @@
#include <nvgpu/gr/setup.h>
#include <nvgpu/gr/fecs_trace.h>
#include "hal/mc/mc_gm20b.h"
#include "hal/mc/mc_gp10b.h"
#include "hal/bus/bus_gk20a.h"
#include "hal/bus/bus_gm20b.h"
#include "hal/bus/bus_gp10b.h"
@@ -86,8 +88,6 @@
#include "common/ptimer/ptimer_gk20a.h"
#include "common/netlist/netlist_gp10b.h"
#include "common/mc/mc_gm20b.h"
#include "common/mc/mc_gp10b.h"
#include "common/perf/perf_gm20b.h"
#include "common/pmu/pmu_gk20a.h"
#include "common/pmu/pmu_gm20b.h"

8
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -22,6 +22,10 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "hal/mc/mc_gm20b.h"
#include "hal/mc/mc_gp10b.h"
#include "hal/mc/mc_gv11b.h"
#include "hal/mc/mc_gv100.h"
#include "hal/bus/bus_gk20a.h"
#include "hal/bus/bus_gp10b.h"
#include "hal/bus/bus_gv100.h"
@@ -87,10 +91,6 @@
#include "common/top/top_gm20b.h"
#include "common/top/top_gp10b.h"
#include "common/top/top_gv100.h"
#include "common/mc/mc_gm20b.h"
#include "common/mc/mc_gp10b.h"
#include "common/mc/mc_gv11b.h"
#include "common/mc/mc_gv100.h"
#include "common/perf/perf_gv11b.h"
#include "common/pmu/pmu_gk20a.h"
#include "common/pmu/pmu_gm20b.h"

6
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -26,6 +26,9 @@
#include <nvgpu/regops.h>
#include <nvgpu/gr/gr_falcon.h>
#include "hal/mc/mc_gm20b.h"
#include "hal/mc/mc_gp10b.h"
#include "hal/mc/mc_gv11b.h"
#include "hal/bus/bus_gk20a.h"
#include "hal/bus/bus_gp10b.h"
#include "hal/bus/bus_gm20b.h"
@@ -83,9 +86,6 @@
#include "common/ptimer/ptimer_gk20a.h"
#include "common/netlist/netlist_gv11b.h"
#include "common/mc/mc_gm20b.h"
#include "common/mc/mc_gp10b.h"
#include "common/mc/mc_gv11b.h"
#include "common/perf/perf_gv11b.h"
#include "common/pmu/pmu_gk20a.h"
#include "common/pmu/pmu_gm20b.h"

2
drivers/gpu/nvgpu/hal/fb/fb_tu104.c
View File

@@ -33,7 +33,7 @@
#include "hal/fb/fb_gv11b.h"
#include "hal/fb/fb_gv100.h"
#include "common/mc/mc_tu104.h"
#include "hal/mc/mc_tu104.h"
#include "tu104/func_tu104.h"

120
drivers/gpu/nvgpu/common/mc/mc_gm20b.c → drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
View File

@@ -40,32 +40,34 @@
void gm20b_mc_isr_stall(struct gk20a *g)
{
u32 mc_intr_0;
u32 engine_id_idx;
u32 active_engine_id = 0;
u32 eng_id;
u32 act_eng_id = 0U;
enum nvgpu_fifo_engine engine_enum;
mc_intr_0 = g->ops.mc.intr_stall(g);
nvgpu_log(g, gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
nvgpu_log(g, gpu_dbg_intr, "stall intr %08x", mc_intr_0);
for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
active_engine_id = g->fifo.active_engines_list[engine_id_idx];
for (eng_id = 0U; eng_id < g->fifo.num_engines; eng_id++) {
act_eng_id = g->fifo.active_engines_list[eng_id];
if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) {
engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
/* GR Engine */
if (engine_enum == NVGPU_ENGINE_GR_GK20A) {
nvgpu_pg_elpg_protected_call(g, gk20a_gr_isr(g));
}
if ((mc_intr_0 &
g->fifo.engine_info[act_eng_id].intr_mask) == 0U) {
continue;
}
engine_enum = g->fifo.engine_info[act_eng_id].engine_enum;
/* GR Engine */
if (engine_enum == NVGPU_ENGINE_GR_GK20A) {
nvgpu_pg_elpg_protected_call(g, gk20a_gr_isr(g));
}
/* CE Engine */
if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) ||
/* CE Engine */
if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) ||
(engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) &&
(g->ops.ce2.isr_stall != NULL)) {
g->ops.ce2.isr_stall(g,
g->fifo.engine_info[active_engine_id].inst_id,
g->fifo.engine_info[active_engine_id].pri_base);
}
g->ops.ce2.isr_stall(g,
g->fifo.engine_info[act_eng_id].inst_id,
g->fifo.engine_info[act_eng_id].pri_base);
}
}
if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) {
@@ -87,10 +89,10 @@ void gm20b_mc_isr_stall(struct gk20a *g)
u32 gm20b_mc_isr_nonstall(struct gk20a *g)
{
u32 ops = 0;
u32 ops = 0U;
u32 mc_intr_1;
u32 engine_id_idx;
u32 active_engine_id = 0;
u32 eng_id;
u32 act_eng_id = 0U;
enum nvgpu_fifo_engine engine_enum;
mc_intr_1 = g->ops.mc.intr_nonstall(g);
@@ -99,12 +101,11 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g)
ops |= g->ops.fifo.intr_1_isr(g);
}
for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines;
engine_id_idx++) {
for (eng_id = 0U; eng_id < g->fifo.num_engines; eng_id++) {
struct fifo_engine_info_gk20a *engine_info;
active_engine_id = g->fifo.active_engines_list[engine_id_idx];
engine_info = &g->fifo.engine_info[active_engine_id];
act_eng_id = g->fifo.active_engines_list[eng_id];
engine_info = &g->fifo.engine_info[act_eng_id];
if ((mc_intr_1 & engine_info->intr_mask) != 0U) {
engine_enum = engine_info->engine_enum;
@@ -138,19 +139,19 @@ void gm20b_mc_intr_enable(struct gk20a *g)
{
u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
gk20a_writel(g, mc_intr_mask_1_r(),
nvgpu_writel(g, mc_intr_mask_1_r(),
mc_intr_pfifo_pending_f()
| eng_intr_mask);
gk20a_writel(g, mc_intr_en_1_r(),
nvgpu_writel(g, mc_intr_en_1_r(),
mc_intr_en_1_inta_hardware_f());
gk20a_writel(g, mc_intr_mask_0_r(),
nvgpu_writel(g, mc_intr_mask_0_r(),
mc_intr_pfifo_pending_f()
| mc_intr_priv_ring_pending_f()
| mc_intr_ltc_pending_f()
| mc_intr_pbus_pending_f()
| eng_intr_mask);
gk20a_writel(g, mc_intr_en_0_r(),
nvgpu_writel(g, mc_intr_en_0_r(),
mc_intr_en_0_inta_hardware_f());
}
@@ -161,72 +162,72 @@ void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable,
mc_intr_mask_1_r());
if (enable) {
gk20a_writel(g, mask_reg,
gk20a_readl(g, mask_reg) |
nvgpu_writel(g, mask_reg,
nvgpu_readl(g, mask_reg) |
mask);
} else {
gk20a_writel(g, mask_reg,
gk20a_readl(g, mask_reg) &
nvgpu_writel(g, mask_reg,
nvgpu_readl(g, mask_reg) &
~mask);
}
}
void gm20b_mc_intr_stall_pause(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_0_r(),
nvgpu_writel(g, mc_intr_en_0_r(),
mc_intr_en_0_inta_disabled_f());
/* flush previous write */
(void) gk20a_readl(g, mc_intr_en_0_r());
(void) nvgpu_readl(g, mc_intr_en_0_r());
}
void gm20b_mc_intr_stall_resume(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_0_r(),
nvgpu_writel(g, mc_intr_en_0_r(),
mc_intr_en_0_inta_hardware_f());
/* flush previous write */
(void) gk20a_readl(g, mc_intr_en_0_r());
(void) nvgpu_readl(g, mc_intr_en_0_r());
}
void gm20b_mc_intr_nonstall_pause(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_1_r(),
nvgpu_writel(g, mc_intr_en_1_r(),
mc_intr_en_0_inta_disabled_f());
/* flush previous write */
(void) gk20a_readl(g, mc_intr_en_1_r());
(void) nvgpu_readl(g, mc_intr_en_1_r());
}
void gm20b_mc_intr_nonstall_resume(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_1_r(),
nvgpu_writel(g, mc_intr_en_1_r(),
mc_intr_en_0_inta_hardware_f());
/* flush previous write */
(void) gk20a_readl(g, mc_intr_en_1_r());
(void) nvgpu_readl(g, mc_intr_en_1_r());
}
u32 gm20b_mc_intr_stall(struct gk20a *g)
{
return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
return nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
}
u32 gm20b_mc_intr_nonstall(struct gk20a *g)
{
return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING));
return nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING));
}
void gm20b_mc_disable(struct gk20a *g, u32 units)
{
u32 pmc;
nvgpu_log(g, gpu_dbg_info, "pmc disable: %08x\n", units);
nvgpu_log(g, gpu_dbg_info, "pmc disable: %08x", units);
nvgpu_spinlock_acquire(&g->mc_enable_lock);
pmc = gk20a_readl(g, mc_enable_r());
pmc = nvgpu_readl(g, mc_enable_r());
pmc &= ~units;
gk20a_writel(g, mc_enable_r(), pmc);
nvgpu_writel(g, mc_enable_r(), pmc);
nvgpu_spinlock_release(&g->mc_enable_lock);
}
@@ -234,25 +235,25 @@ void gm20b_mc_enable(struct gk20a *g, u32 units)
{
u32 pmc;
nvgpu_log(g, gpu_dbg_info, "pmc enable: %08x\n", units);
nvgpu_log(g, gpu_dbg_info, "pmc enable: %08x", units);
nvgpu_spinlock_acquire(&g->mc_enable_lock);
pmc = gk20a_readl(g, mc_enable_r());
pmc = nvgpu_readl(g, mc_enable_r());
pmc |= units;
gk20a_writel(g, mc_enable_r(), pmc);
pmc = gk20a_readl(g, mc_enable_r());
nvgpu_writel(g, mc_enable_r(), pmc);
pmc = nvgpu_readl(g, mc_enable_r());
nvgpu_spinlock_release(&g->mc_enable_lock);
nvgpu_udelay(20);
nvgpu_udelay(MC_ENABLE_DELAY_US);
}
void gm20b_mc_reset(struct gk20a *g, u32 units)
{
g->ops.mc.disable(g, units);
if ((units & nvgpu_engine_get_all_ce_reset_mask(g)) != 0U) {
nvgpu_udelay(500);
nvgpu_udelay(MC_RESET_CE_DELAY_US);
} else {
nvgpu_udelay(20);
nvgpu_udelay(MC_RESET_DELAY_US);
}
g->ops.mc.enable(g, units);
}
@@ -275,7 +276,7 @@ bool gm20b_mc_is_intr1_pending(struct gk20a *g,
nvgpu_err(g, "unknown unit %d", unit);
is_pending = false;
} else {
is_pending = ((mc_intr_1 & mask) != 0U) ? true : false;
is_pending = ((mc_intr_1 & mask) != 0U);
}
return is_pending;
@@ -306,9 +307,9 @@ void gm20b_mc_log_pending_intrs(struct gk20a *g)
u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
{
u32 mask = 0;
u32 mask = 0U;
switch(unit) {
switch (unit) {
case NVGPU_UNIT_FIFO:
mask = mc_enable_pfifo_enabled_f();
break;
@@ -325,8 +326,7 @@ u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
mask = mc_enable_pwr_enabled_f();
break;
default:
nvgpu_err(g, "unknown reset unit %d", unit);
BUG();
WARN(1, "unknown reset unit %d", unit);
break;
}
@@ -346,11 +346,11 @@ void gm20b_mc_fb_reset(struct gk20a *g)
nvgpu_log_info(g, "reset gk20a fb");
val = gk20a_readl(g, mc_elpg_enable_r());
val = nvgpu_readl(g, mc_elpg_enable_r());
val |= mc_elpg_enable_xbar_enabled_f()
| mc_elpg_enable_pfb_enabled_f()
| mc_elpg_enable_hub_enabled_f();
gk20a_writel(g, mc_elpg_enable_r(), val);
nvgpu_writel(g, mc_elpg_enable_r(), val);
}
void gm20b_mc_ltc_isr(struct gk20a *g)
@@ -358,7 +358,7 @@ void gm20b_mc_ltc_isr(struct gk20a *g)
u32 mc_intr;
u32 ltc;
mc_intr = gk20a_readl(g, mc_intr_ltc_r());
mc_intr = nvgpu_readl(g, mc_intr_ltc_r());
nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr);
for (ltc = 0; ltc < nvgpu_ltc_get_ltc_count(g); ltc++) {
if ((mc_intr & BIT32(ltc)) == 0U) {

14
drivers/gpu/nvgpu/common/mc/mc_gm20b.h → drivers/gpu/nvgpu/hal/mc/mc_gm20b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,10 @@
#include <nvgpu/types.h>
#define MC_ENABLE_DELAY_US 20U
#define MC_RESET_DELAY_US 20U
#define MC_RESET_CE_DELAY_US 500U
struct gk20a;
enum nvgpu_unit;
@@ -33,11 +37,11 @@ void gm20b_mc_intr_enable(struct gk20a *g);
void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable,
bool is_stalling, u32 mask);
void gm20b_mc_isr_stall(struct gk20a *g);
u32 gm20b_mc_intr_stall(struct gk20a *g);
u32 gm20b_mc_intr_stall(struct gk20a *g);
void gm20b_mc_intr_stall_pause(struct gk20a *g);
void gm20b_mc_intr_stall_resume(struct gk20a *g);
u32 gm20b_mc_intr_nonstall(struct gk20a *g);
u32 gm20b_mc_isr_nonstall(struct gk20a *g);
u32 gm20b_mc_intr_nonstall(struct gk20a *g);
u32 gm20b_mc_isr_nonstall(struct gk20a *g);
void gm20b_mc_intr_nonstall_pause(struct gk20a *g);
void gm20b_mc_intr_nonstall_resume(struct gk20a *g);
void gm20b_mc_enable(struct gk20a *g, u32 units);
@@ -47,7 +51,7 @@ bool gm20b_mc_is_intr1_pending(struct gk20a *g,
enum nvgpu_unit unit, u32 mc_intr_1);
void gm20b_mc_log_pending_intrs(struct gk20a *g);
void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops);
u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit);
void gm20b_mc_fb_reset(struct gk20a *g);
void gm20b_mc_ltc_isr(struct gk20a *g);

89
drivers/gpu/nvgpu/common/mc/mc_gp10b.c → drivers/gpu/nvgpu/hal/mc/mc_gp10b.c
View File

@@ -36,23 +36,21 @@
#include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
#define MAX_MC_INTR_REGS 2U
void mc_gp10b_intr_mask(struct gk20a *g)
{
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffffU);
U32_MAX);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
U32_MAX);
}
void mc_gp10b_intr_enable(struct gk20a *g)
{
u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffffU);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
U32_MAX);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f() |
mc_intr_priv_ring_pending_f() |
@@ -60,23 +58,23 @@ void mc_gp10b_intr_enable(struct gk20a *g)
mc_intr_ltc_pending_f() |
mc_intr_replayable_fault_pending_f() |
eng_intr_mask;
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
U32_MAX);
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
mc_intr_pfifo_pending_f() |
eng_intr_mask;
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
}
void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
bool is_stalling, u32 mask)
{
u32 intr_index = 0;
u32 reg = 0;
u32 intr_index = 0U;
u32 reg = 0U;
intr_index = (is_stalling ? NVGPU_MC_INTR_STALLING :
NVGPU_MC_INTR_NONSTALLING);
@@ -89,39 +87,40 @@ void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
g->mc_intr_mask_restore[intr_index] &= ~mask;
}
gk20a_writel(g, reg, mask);
nvgpu_writel(g, reg, mask);
}
void mc_gp10b_isr_stall(struct gk20a *g)
{
u32 mc_intr_0;
u32 engine_id_idx;
u32 active_engine_id = 0;
u32 eng_id;
u32 act_eng_id = 0U;
enum nvgpu_fifo_engine engine_enum;
mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
mc_intr_0 = nvgpu_readl(g, mc_intr_r(0));
nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x\n", mc_intr_0);
nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x", mc_intr_0);
for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
active_engine_id = g->fifo.active_engines_list[engine_id_idx];
for (eng_id = 0U; eng_id < g->fifo.num_engines; eng_id++) {
act_eng_id = g->fifo.active_engines_list[eng_id];
if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) {
engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
/* GR Engine */
if (engine_enum == NVGPU_ENGINE_GR_GK20A) {
nvgpu_pg_elpg_protected_call(g, gk20a_gr_isr(g));
}
if ((mc_intr_0 &
g->fifo.engine_info[act_eng_id].intr_mask) == 0U) {
continue;
}
engine_enum = g->fifo.engine_info[act_eng_id].engine_enum;
/* GR Engine */
if (engine_enum == NVGPU_ENGINE_GR_GK20A) {
nvgpu_pg_elpg_protected_call(g, gk20a_gr_isr(g));
}
/* CE Engine */
if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) ||
/* CE Engine */
if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) ||
(engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) &&
(g->ops.ce2.isr_stall != NULL)) {
g->ops.ce2.isr_stall(g,
g->fifo.engine_info[active_engine_id].inst_id,
g->fifo.engine_info[active_engine_id].pri_base);
}
g->ops.ce2.isr_stall(g,
g->fifo.engine_info[act_eng_id].inst_id,
g->fifo.engine_info[act_eng_id].pri_base);
}
}
if ((g->ops.mc.is_intr_hub_pending != NULL) &&
@@ -152,47 +151,47 @@ void mc_gp10b_isr_stall(struct gk20a *g)
g->ops.mc.fbpa_isr(g);
}
nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0);
nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x", mc_intr_0);
}
u32 mc_gp10b_intr_stall(struct gk20a *g)
{
return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
return nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
}
void mc_gp10b_intr_stall_pause(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 0xffffffffU);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), U32_MAX);
}
void mc_gp10b_intr_stall_resume(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
}
u32 mc_gp10b_intr_nonstall(struct gk20a *g)
{
return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING));
return nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING));
}
void mc_gp10b_intr_nonstall_pause(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
U32_MAX);
}
void mc_gp10b_intr_nonstall_resume(struct gk20a *g)
{
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
}
bool mc_gp10b_is_intr1_pending(struct gk20a *g,
enum nvgpu_unit unit, u32 mc_intr_1)
{
u32 mask = 0;
u32 mask = 0U;
bool is_pending;
switch (unit) {
@@ -207,7 +206,7 @@ bool mc_gp10b_is_intr1_pending(struct gk20a *g,
nvgpu_err(g, "unknown unit %d", unit);
is_pending = false;
} else {
is_pending = ((mc_intr_1 & mask) != 0U) ? true : false;
is_pending = ((mc_intr_1 & mask) != 0U);
}
return is_pending;
@@ -217,7 +216,7 @@ void mc_gp10b_log_pending_intrs(struct gk20a *g)
{
u32 i, intr;
for (i = 0; i < MAX_MC_INTR_REGS; i++) {
for (i = 0U; i < MAX_MC_INTR_REGS; i++) {
intr = nvgpu_readl(g, mc_intr_r(i));
if (intr == 0U) {
continue;
@@ -232,9 +231,9 @@ void mc_gp10b_ltc_isr(struct gk20a *g)
u32 mc_intr;
u32 ltc;
mc_intr = gk20a_readl(g, mc_intr_ltc_r());
mc_intr = nvgpu_readl(g, mc_intr_ltc_r());
nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr);
for (ltc = 0; ltc < nvgpu_ltc_get_ltc_count(g); ltc++) {
for (ltc = 0U; ltc < nvgpu_ltc_get_ltc_count(g); ltc++) {
if ((mc_intr & BIT32(ltc)) == 0U) {
continue;
}

8
drivers/gpu/nvgpu/common/mc/mc_gp10b.h → drivers/gpu/nvgpu/hal/mc/mc_gp10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,8 @@
#include <nvgpu/types.h>
#define MAX_MC_INTR_REGS 2U
struct gk20a;
enum nvgpu_unit;
@@ -37,10 +39,10 @@ bool mc_gp10b_is_intr1_pending(struct gk20a *g,
enum nvgpu_unit unit, u32 mc_intr_1);
void mc_gp10b_log_pending_intrs(struct gk20a *g);
u32 mc_gp10b_intr_stall(struct gk20a *g);
u32 mc_gp10b_intr_stall(struct gk20a *g);
void mc_gp10b_intr_stall_pause(struct gk20a *g);
void mc_gp10b_intr_stall_resume(struct gk20a *g);
u32 mc_gp10b_intr_nonstall(struct gk20a *g);
u32 mc_gp10b_intr_nonstall(struct gk20a *g);
void mc_gp10b_intr_nonstall_pause(struct gk20a *g);
void mc_gp10b_intr_nonstall_resume(struct gk20a *g);
void mc_gp10b_ltc_isr(struct gk20a *g);

25
drivers/gpu/nvgpu/common/mc/mc_gv100.c → drivers/gpu/nvgpu/hal/mc/mc_gv100.c
View File

@@ -1,7 +1,7 @@
/*
* GV100 master
*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -39,10 +39,10 @@ void mc_gv100_intr_enable(struct gk20a *g)
{
u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffffU);
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
U32_MAX);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
U32_MAX);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f() |
mc_intr_hub_pending_f() |
@@ -56,23 +56,23 @@ void mc_gv100_intr_enable(struct gk20a *g)
mc_intr_pfifo_pending_f()
| eng_intr_mask;
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
}
bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0)
{
return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false);
return ((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U);
}
bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
u32 *eng_intr_pending)
{
u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
u32 mc_intr_0 = nvgpu_readl(g, mc_intr_r(0));
u32 stall_intr, eng_intr_mask;
eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, act_eng_id);
@@ -94,9 +94,9 @@ bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
{
u32 mask = 0;
u32 mask = 0U;
switch(unit) {
switch (unit) {
case NVGPU_UNIT_FIFO:
mask = mc_enable_pfifo_enabled_f();
break;
@@ -116,8 +116,7 @@ u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
mask = mc_enable_nvdec_enabled_f();
break;
default:
nvgpu_err(g, "unknown reset unit %d", unit);
BUG();
WARN(1, "unknown reset unit %d", unit);
break;
}

4
drivers/gpu/nvgpu/common/mc/mc_gv100.h → drivers/gpu/nvgpu/hal/mc/mc_gv100.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -31,6 +31,6 @@ void mc_gv100_intr_enable(struct gk20a *g);
bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0);
bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
u32 *eng_intr_pending);
u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
#endif

18
drivers/gpu/nvgpu/common/mc/mc_gv11b.c → drivers/gpu/nvgpu/hal/mc/mc_gv11b.c
View File

@@ -1,7 +1,7 @@
/*
* GV11B master
*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -37,10 +37,10 @@ void mc_gv11b_intr_enable(struct gk20a *g)
{
u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffffU);
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
U32_MAX);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
U32_MAX);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f() |
@@ -54,23 +54,23 @@ void mc_gv11b_intr_enable(struct gk20a *g)
mc_intr_pfifo_pending_f()
| eng_intr_mask;
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
}
bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)
{
return (((mc_intr_0 & mc_intr_hub_pending_f()) != 0U) ? true : false);
return ((mc_intr_0 & mc_intr_hub_pending_f()) != 0U);
}
bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
u32 *eng_intr_pending)
{
u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
u32 mc_intr_0 = nvgpu_readl(g, mc_intr_r(0));
u32 stall_intr, eng_intr_mask;
eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, act_eng_id);

2
drivers/gpu/nvgpu/common/mc/mc_gv11b.h → drivers/gpu/nvgpu/hal/mc/mc_gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

40
drivers/gpu/nvgpu/common/mc/mc_tu104.c → drivers/gpu/nvgpu/hal/mc/mc_tu104.c
View File

@@ -28,7 +28,8 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/engines.h>
#include "common/mc/mc_gp10b.h"
#include "hal/mc/mc_gp10b.h"
#include "mc_tu104.h"
#include "tu104/func_tu104.h"
@@ -138,8 +139,7 @@ static void intr_tu104_stall_enable(struct gk20a *g)
{
u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffffU);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), U32_MAX);
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f() |
@@ -162,8 +162,7 @@ static void intr_tu104_nonstall_enable(struct gk20a *g)
u32 active_engine_id, intr_mask;
/* Keep NV_PMC_INTR(1) disabled */
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), U32_MAX);
/*
* Enable nonstall interrupts in TOP
@@ -206,16 +205,14 @@ void intr_tu104_mask(struct gk20a *g)
{
u32 size, reg, i;
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffffU);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), U32_MAX);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffffU);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), U32_MAX);
size = func_priv_cpu_intr_top_en_clear__size_1_v();
for (i = 0; i < size; i++) {
for (i = 0U; i < size; i++) {
reg = func_priv_cpu_intr_top_en_clear_r(i);
nvgpu_func_writel(g, reg, 0xffffffffU);
nvgpu_func_writel(g, reg, U32_MAX);
}
}
@@ -270,12 +267,12 @@ void intr_tu104_nonstall_resume(struct gk20a *g)
u32 intr_tu104_isr_nonstall(struct gk20a *g)
{
u32 i;
u32 nonstall_intr_base = 0;
u64 nonstall_intr_mask = 0;
u32 nonstall_intr_base = 0U;
u64 nonstall_intr_mask = 0U;
u32 nonstall_intr_mask_lo, nonstall_intr_mask_hi;
u32 intr_leaf_reg0, intr_leaf_reg1;
u32 active_engine_id, intr_mask;
u32 ops = 0;
u32 ops = 0U;
intr_leaf_reg0 = nvgpu_func_readl(g,
func_priv_cpu_intr_leaf_r(
@@ -290,7 +287,7 @@ u32 intr_tu104_isr_nonstall(struct gk20a *g)
nonstall_intr_base = nvgpu_readl(g,
ctrl_legacy_engine_nonstall_intr_base_vectorid_r());
for (i = 0; i < g->fifo.num_engines; i++) {
for (i = 0U; i < g->fifo.num_engines; i++) {
active_engine_id = g->fifo.active_engines_list[i];
intr_mask = g->fifo.engine_info[active_engine_id].intr_mask;
@@ -300,7 +297,8 @@ u32 intr_tu104_isr_nonstall(struct gk20a *g)
if ((nonstall_intr_mask_lo & intr_leaf_reg0) != 0U ||
(nonstall_intr_mask_hi & intr_leaf_reg1) != 0U) {
nvgpu_log(g, gpu_dbg_intr, "nonstall intr from engine %d",
nvgpu_log(g, gpu_dbg_intr,
"nonstall intr from engine %d",
active_engine_id);
nvgpu_func_writel(g,
@@ -337,7 +335,7 @@ u32 intr_tu104_stall(struct gk20a *g)
return g->ops.mc.is_intr_hub_pending(g, 0);
}
return 0;
return 0U;
}
/* Return true if HUB interrupt is pending */
@@ -362,8 +360,6 @@ void intr_tu104_stall_resume(struct gk20a *g)
g->ops.fb.enable_hub_intr(g);
}
#define MAX_INTR_TOP_REGS (2U)
void intr_tu104_log_pending_intrs(struct gk20a *g)
{
bool pending;
@@ -386,7 +382,7 @@ void intr_tu104_log_pending_intrs(struct gk20a *g)
}
}
for (i = 0; i < MAX_INTR_TOP_REGS; i++) {
for (i = 0U; i < MAX_INTR_TOP_REGS; i++) {
intr = nvgpu_func_readl(g,
func_priv_cpu_intr_top_r(i));
if (intr == 0U) {
@@ -401,11 +397,11 @@ void mc_tu104_fbpa_isr(struct gk20a *g)
u32 intr_fbpa, fbpas;
u32 i, num_fbpas;
intr_fbpa = gk20a_readl(g, mc_intr_fbpa_r());
intr_fbpa = nvgpu_readl(g, mc_intr_fbpa_r());
fbpas = mc_intr_fbpa_part_mask_v(intr_fbpa);
num_fbpas = nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPAS);
for (i = 0u; i < num_fbpas; i++) {
for (i = 0U; i < num_fbpas; i++) {
if ((fbpas & BIT32(i)) == 0U) {
continue;
}

16
drivers/gpu/nvgpu/common/mc/mc_tu104.h → drivers/gpu/nvgpu/hal/mc/mc_tu104.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,14 +25,16 @@
#include <nvgpu/types.h>
#define MAX_INTR_TOP_REGS (2U)
#define NV_CPU_INTR_SUBTREE_TO_TOP_IDX(i) ((i) / 32U)
#define NV_CPU_INTR_SUBTREE_TO_TOP_BIT(i) ((i) % 32U)
#define NV_CPU_INTR_SUBTREE_TO_LEAF_REG0(i) ((i)*2U)
#define NV_CPU_INTR_SUBTREE_TO_LEAF_REG1(i) (((i)*2U) + 1U)
#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i) ((i) / 32U)
#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(i) ((i) % 32U)
#define NV_CPU_INTR_GPU_VECTOR_TO_SUBTREE(i) ((NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2U)
#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i) ((i) / 32U)
#define NV_CPU_INTR_GPU_VECTOR_TO_LEAF_BIT(i) ((i) % 32U)
#define NV_CPU_INTR_GPU_VECTOR_TO_SUBTREE(i) ((NV_CPU_INTR_GPU_VECTOR_TO_LEAF_REG(i)) / 2U)
#define NV_CPU_INTR_TOP_NONSTALL_SUBTREE 0U
@@ -51,13 +53,13 @@ void intr_tu104_intr_clear_leaf_vector(struct gk20a *g, u32 intr_vector);
void intr_tu104_mask(struct gk20a *g);
void intr_tu104_enable(struct gk20a *g);
u32 intr_tu104_stall(struct gk20a *g);
u32 intr_tu104_stall(struct gk20a *g);
void intr_tu104_stall_pause(struct gk20a *g);
void intr_tu104_stall_resume(struct gk20a *g);
u32 intr_tu104_nonstall(struct gk20a *g);
u32 intr_tu104_nonstall(struct gk20a *g);
void intr_tu104_nonstall_pause(struct gk20a *g);
void intr_tu104_nonstall_resume(struct gk20a *g);
u32 intr_tu104_isr_nonstall(struct gk20a *g);
u32 intr_tu104_isr_nonstall(struct gk20a *g);
bool intr_tu104_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0);
void intr_tu104_log_pending_intrs(struct gk20a *g);
void mc_tu104_fbpa_isr(struct gk20a *g);

10
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -22,6 +22,11 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "hal/mc/mc_gm20b.h"
#include "hal/mc/mc_gp10b.h"
#include "hal/mc/mc_gv11b.h"
#include "hal/mc/mc_gv100.h"
#include "hal/mc/mc_tu104.h"
#include "hal/bus/bus_gk20a.h"
#include "hal/bus/bus_gp10b.h"
#include "hal/bus/bus_gv100.h"
@@ -90,11 +95,6 @@
#include "common/ptimer/ptimer_gk20a.h"
#include "common/xve/xve_gp106.h"
#include "common/netlist/netlist_tu104.h"
#include "common/mc/mc_gm20b.h"
#include "common/mc/mc_gp10b.h"
#include "common/mc/mc_gv11b.h"
#include "common/mc/mc_gv100.h"
#include "common/mc/mc_tu104.h"
#include "common/perf/perf_gv11b.h"
#include "common/pmu/pmu_gk20a.h"
#include "common/pmu/pmu_gm20b.h"