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0e367046e9b372272eb9f92cbd6c96c02d475670
linux-nvgpu/drivers/gpu/nvgpu/gk20a
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Philip Elcan 1c7bb9b538 gpu: nvgpu: channel: make chid u32 
The chid member of the channel_gk20a struct was being used as a unsigned
value. By being declared as an int, it was causing MISRA 10.3 violations
for implicit assignment of different types.

JIRA NVGPU-647

Change-Id: I7477fad6f0c837cf7ede1dba803158b1dda717af
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1918470
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-16 16:47:17 -07:00
..
ce2_gk20a.c
gpu: nvgpu: fix circular dep of ce2 and gk20a headers
2018-10-12 17:35:11 +05:30
ce2_gk20a.h
gpu: nvgpu: fix circular dep of ce2 and gk20a headers
2018-10-12 17:35:11 +05:30
clk_gk20a.h
gpu: nvgpu: cache gpu clk rate
2018-04-23 12:12:52 -07:00
dbg_gpu_gk20a.c
gpu: nvgpu: MISRA 14.4 err/ret/status as boolean
2018-10-12 17:35:11 +05:30
dbg_gpu_gk20a.h
gpu: nvgpu: channel: make chid u32
2018-10-16 16:47:17 -07:00
fecs_trace_gk20a.c
gpu: nvgpu: MISRA 14.4 err/ret/status as boolean
2018-10-12 17:35:11 +05:30
fecs_trace_gk20a.h
nvgpu: gk20a: MISRA Rule 21.2 header guard fixes
2018-09-06 16:15:30 -07:00
fence_gk20a.c
gpu: nvgpu: MISRA 14.4 err/ret/status as boolean
2018-10-12 17:35:11 +05:30
fence_gk20a.h
nvgpu: gk20a: MISRA Rule 21.2 header guard fixes
2018-09-06 16:15:30 -07:00
fifo_gk20a.c
gpu: nvgpu: channel: make chid u32
2018-10-16 16:47:17 -07:00
fifo_gk20a.h
gpu: nvgpu: fifo_gk20: make pbdma_id type the same
2018-10-16 16:46:42 -07:00
flcn_gk20a.c
gpu: nvgpu: add GSP falcon support
2018-09-24 21:17:29 -07:00
flcn_gk20a.h
nvgpu: gk20a: MISRA Rule 21.2 header guard fixes
2018-09-06 16:15:30 -07:00
gk20a.c
gpu: nvgpu: Remove cyclic dependency PMU<->GR.
2018-10-16 05:54:55 -07:00
gk20a.h
gpu: nvgpu: Move MC HAL to common
2018-09-13 19:18:24 -07:00
gr_ctx_gk20a_sim.c
gpu: nvgpu: gk20a: Fix MISRA 15.6 violations
2018-08-06 17:36:39 -07:00
gr_ctx_gk20a.c
gpu: nvgpu: MISRA 14.4 err/ret/status as boolean
2018-10-12 17:35:11 +05:30
gr_ctx_gk20a.h
nvgpu: gk20a: MISRA Rule 21.2 header guard fixes
2018-09-06 16:15:30 -07:00
gr_gk20a.c
gpu: nvgpu: channel: make chid u32
2018-10-16 16:47:17 -07:00
gr_gk20a.h
gpu: nvgpu: Move programming of debug page to FB
2018-09-10 15:23:12 -07:00
gr_pri_gk20a.h
nvgpu: gk20a: gr: MISRA 10.1 & 14.4 boolean fixes
2018-09-19 03:24:16 -07:00
mm_gk20a.c
gpu: nvgpu: MISRA 14.4 err/ret/status as boolean
2018-10-12 17:35:11 +05:30
mm_gk20a.h
gpu: nvgpu: move priv cmd definitions to channel
2018-08-30 21:42:57 -07:00
pmu_gk20a.c
gpu: nvgpu: Add MC APIs for reset masks
2018-10-12 17:35:07 +05:30
pmu_gk20a.h
gpu: nvgpu: PMU init sequence change
2018-09-24 08:12:03 -07:00
regops_gk20a.c
gpu: nvgpu: MISRA 14.4 err/ret/status as boolean
2018-10-12 17:35:11 +05:30
regops_gk20a.h
gpu: nvgpu: Return gr_ctx_resident from NVGPU_DBG_GPU_IOCTL_REG_OPS
2018-09-09 17:23:06 -07:00