gpu: nvgpu: fix circular dep of ce2 and gk20a headers

struct gk20a from gk20a.h needs defination of struct gk20a_ce_app
and ce2_gk20a.h needs defination of struct gk20a. This creates
a circular dependency.

Fix this by making gk20a_ce_app a pointer to skip knowing the
complete type details and using forward declarations for struct
gk20a_ce_app and struct gk20a.

The gk20a_ce_app pointer is alloc'ed in gk20a_init_ce_support()
and free'ed in gk20a_ce_destroy.

JIRA NVGPU-611

Change-Id: I4d62d5f2b2d1492db73bae69f90a1fe5586fba76
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917945
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/ce2.c

@@ -53,7 +53,7 @@ int gk20a_ce_execute_ops(struct gk20a *g,
 		struct gk20a_fence **gk20a_fence_out)
 {
 	int ret = -EPERM;
-	struct gk20a_ce_app *ce_app = &g->ce_app;
+	struct gk20a_ce_app *ce_app = g->ce_app;
 	struct gk20a_gpu_ctx *ce_ctx, *ce_ctx_save;
 	bool found = false;
 	u32 *cmd_buf_cpu_va;

drivers/gpu/nvgpu/common/mm/mm.c

@@ -31,6 +31,8 @@
 #include <nvgpu/enabled.h>
 #include <nvgpu/gk20a.h>
 
+#include "gk20a/ce2_gk20a.h"
+
 /*
  * Attempt to find a reserved memory area to determine PTE size for the passed
  * mapping. If no reserved area can be found use small pages.

drivers/gpu/nvgpu/common/mm/vidmem.c

@@ -31,6 +31,7 @@
 
 #include "gk20a/mm_gk20a.h"
 #include "gk20a/fence_gk20a.h"
+#include "gk20a/ce2_gk20a.h"
 
 /*
  * This is expected to be called from the shutdown path (or the error path in

drivers/gpu/nvgpu/gk20a/ce2_gk20a.c

@@ -33,6 +33,7 @@
 
 #include "gk20a.h"
 #include "gk20a/fence_gk20a.h"
+#include "gk20a/ce2_gk20a.h"
 
 #include <nvgpu/hw/gk20a/hw_ce2_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h>
@@ -331,10 +332,18 @@ int gk20a_ce_prepare_submit(u64 src_buf,
 /* global CE app related apis */
 int gk20a_init_ce_support(struct gk20a *g)
 {
-	struct gk20a_ce_app *ce_app = &g->ce_app;
+	struct gk20a_ce_app *ce_app = g->ce_app;
 	int err;
 	u32 ce_reset_mask;
 
+	if (unlikely(ce_app == NULL)) {
+		ce_app = nvgpu_kzalloc(g, sizeof(*ce_app));
+		if (ce_app == NULL) {
+			return -ENOMEM;
+		}
+		g->ce_app = ce_app;
+	}
+
 	ce_reset_mask = gk20a_fifo_get_all_ce_engine_reset_mask(g);
 
 	g->ops.mc.reset(g, ce_reset_mask);
@@ -377,13 +386,17 @@ int gk20a_init_ce_support(struct gk20a *g)
 
 void gk20a_ce_destroy(struct gk20a *g)
 {
-	struct gk20a_ce_app *ce_app = &g->ce_app;
+	struct gk20a_ce_app *ce_app = g->ce_app;
 	struct gk20a_gpu_ctx *ce_ctx, *ce_ctx_save;
 
-	if (!ce_app->initialised) {
+	if (ce_app == NULL) {
 		return;
 	}
 
+	if (ce_app->initialised == false) {
+		goto free;
+	}
+
 	ce_app->app_state = NVGPU_CE_SUSPEND;
 	ce_app->initialised = false;
 
@@ -401,11 +414,13 @@ void gk20a_ce_destroy(struct gk20a *g)
 	nvgpu_mutex_release(&ce_app->app_mutex);
 
 	nvgpu_mutex_destroy(&ce_app->app_mutex);
+free:
+	nvgpu_kfree(g, ce_app);
 }
 
 void gk20a_ce_suspend(struct gk20a *g)
 {
-	struct gk20a_ce_app *ce_app = &g->ce_app;
+	struct gk20a_ce_app *ce_app = g->ce_app;
 
 	if (!ce_app->initialised) {
 		return;
@@ -423,7 +438,7 @@ u32 gk20a_ce_create_context(struct gk20a *g,
 		int runlist_level)
 {
 	struct gk20a_gpu_ctx *ce_ctx;
-	struct gk20a_ce_app *ce_app = &g->ce_app;
+	struct gk20a_ce_app *ce_app = g->ce_app;
 	struct nvgpu_gpfifo_args gpfifo_args;
 	u32 ctx_id = ~0;
 	int err = 0;
@@ -552,7 +567,7 @@ void gk20a_ce_delete_context(struct gk20a *g,
 void gk20a_ce_delete_context_priv(struct gk20a *g,
 		u32 ce_ctx_id)
 {
-	struct gk20a_ce_app *ce_app = &g->ce_app;
+	struct gk20a_ce_app *ce_app = g->ce_app;
 	struct gk20a_gpu_ctx *ce_ctx, *ce_ctx_save;
 
 	if (!ce_app->initialised || ce_app->app_state != NVGPU_CE_ACTIVE) {

drivers/gpu/nvgpu/gk20a/ce2_gk20a.h

@@ -28,6 +28,7 @@
 
 struct channel_gk20a;
 struct tsg_gk20a;
+struct gk20a;
 
 void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
 u32 gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);

drivers/gpu/nvgpu/gk20a/gk20a.c

@@ -43,6 +43,7 @@
 #include <trace/events/gk20a.h>
 
 #include "gk20a.h"
+#include "gk20a/ce2_gk20a.h"
 
 #include "dbg_gpu_gk20a.h"
 #include "pstate/pstate.h"

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -29,6 +29,7 @@ struct fifo_gk20a;
 struct channel_gk20a;
 struct gr_gk20a;
 struct sim_nvgpu;
+struct gk20a_ce_app;
 struct gk20a_ctxsw_ucode_segments;
 struct gk20a_fecs_trace;
 struct gk20a_ctxsw_trace;
@@ -70,7 +71,6 @@ struct nvgpu_gpfifo_args;
 #include <nvgpu/sec2.h>
 
 #include "gk20a/clk_gk20a.h"
-#include "gk20a/ce2_gk20a.h"
 #include "gk20a/fifo_gk20a.h"
 #include "clk/clk.h"
 #include "pmu_perf/pmu_perf.h"
@@ -1631,7 +1631,7 @@ struct gk20a {
 
 	nvgpu_atomic_t clk_arb_global_nr;
 
-	struct gk20a_ce_app ce_app;
+	struct gk20a_ce_app *ce_app;
 
 	bool ltc_intr_en_illegal_compstat;
 

drivers/gpu/nvgpu/os/linux/debug_ce.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017 NVIDIA Corporation.  All rights reserved.
+ * Copyright (C) 2017-2018 NVIDIA Corporation.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -15,6 +15,8 @@
 #include "debug_ce.h"
 #include "os_linux.h"
 
+#include "gk20a/ce2_gk20a.h"
+
 #include <linux/debugfs.h>
 
 void gk20a_ce_debugfs_init(struct gk20a *g)
@@ -22,9 +24,9 @@ void gk20a_ce_debugfs_init(struct gk20a *g)
 	struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
 
 	debugfs_create_u32("ce_app_ctx_count", S_IWUSR | S_IRUGO,
-			   l->debugfs, &g->ce_app.ctx_count);
+			   l->debugfs, &g->ce_app->ctx_count);
 	debugfs_create_u32("ce_app_state", S_IWUSR | S_IRUGO,
-			   l->debugfs, &g->ce_app.app_state);
+			   l->debugfs, &g->ce_app->app_state);
 	debugfs_create_u32("ce_app_next_ctx_id", S_IWUSR | S_IRUGO,
-			   l->debugfs, &g->ce_app.next_ctx_id);
+			   l->debugfs, &g->ce_app->next_ctx_id);
 }