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20d1b9a40d
Updated DFS control settings for GPCPLL revision C1 per characterization data. Bug 1942222 Change-Id: Iab5147e13ef70df980d36589328abafd8f5495b8 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/1502741 (cherry picked from commit 5ea62c9e264de86f6e5a40a7f31054ab31b3196f) Reviewed-on: https://git-master.nvidia.com/r/1525830 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
126 lines
3.0 KiB
C
126 lines
3.0 KiB
C
/*
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* Copyright (c) 2011 - 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CLK_GK20A_H
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#define CLK_GK20A_H
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#include <nvgpu/lock.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#define GPUFREQ_TABLE_END ~(u32)1
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enum {
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/* only one PLL for gk20a */
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GK20A_GPC_PLL = 0,
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/* 2 PLL revisions for gm20b */
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GM20B_GPC_PLL_B1,
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GM20B_GPC_PLL_C1,
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};
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enum gpc_pll_mode {
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GPC_PLL_MODE_F = 0, /* fixed frequency mode a.k.a legacy mode */
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GPC_PLL_MODE_DVFS, /* DVFS mode a.k.a NA mode */
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};
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struct na_dvfs {
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u32 n_int;
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u32 sdm_din;
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int dfs_coeff;
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int dfs_det_max;
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int dfs_ext_cal;
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int uv_cal;
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int mv;
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};
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struct pll {
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u32 id;
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u32 clk_in; /* KHz */
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u32 M;
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u32 N;
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u32 PL;
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u32 freq; /* KHz */
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bool enabled;
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enum gpc_pll_mode mode;
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struct na_dvfs dvfs;
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};
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struct pll_parms {
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u32 min_freq, max_freq; /* KHz */
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u32 min_vco, max_vco; /* KHz */
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u32 min_u, max_u; /* KHz */
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u32 min_M, max_M;
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u32 min_N, max_N;
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u32 min_PL, max_PL;
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/* NA mode parameters*/
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int coeff_slope, coeff_offs; /* coeff = slope * V + offs */
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int uvdet_slope, uvdet_offs; /* uV = slope * det + offs */
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u32 vco_ctrl;
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/*
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* Timing parameters in us. Lock timeout is applied to locking in fixed
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* frequency mode and to dynamic ramp in any mode; does not affect lock
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* latency, since lock/ramp done status bit is polled. NA mode lock and
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* and IDDQ exit delays set the time of the respective opertaions with
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* no status polling.
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*/
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u32 lock_timeout;
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u32 na_lock_delay;
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u32 iddq_exit_delay;
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/* NA mode DFS control */
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u32 dfs_ctrl;
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};
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struct namemap_cfg;
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struct clk_gk20a {
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struct gk20a *g;
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struct clk *tegra_clk;
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#if defined(CONFIG_COMMON_CLK)
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struct clk_hw hw;
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#endif
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struct pll gpc_pll;
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struct pll gpc_pll_last;
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struct nvgpu_mutex clk_mutex;
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struct namemap_cfg *clk_namemap;
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u32 namemap_num;
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u32 *namemap_xlat_table;
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bool sw_ready;
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bool clk_hw_on;
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bool debugfs_set;
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int pll_poweron_uv;
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unsigned long dvfs_safe_max_freq;
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};
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#if defined(CONFIG_COMMON_CLK)
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#define to_clk_gk20a(_hw) container_of(_hw, struct clk_gk20a, hw)
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#endif
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struct gpu_ops;
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#define KHZ 1000
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#define MHZ 1000000
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static inline unsigned long rate_gpc2clk_to_gpu(unsigned long rate)
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{
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/* convert the kHz gpc2clk frequency to Hz gpcpll frequency */
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return (rate * KHZ) / 2;
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}
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static inline unsigned long rate_gpu_to_gpc2clk(unsigned long rate)
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{
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/* convert the Hz gpcpll frequency to kHz gpc2clk frequency */
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return (rate * 2) / KHZ;
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}
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#endif /* CLK_GK20A_H */
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